Contributors
A
Research Manuscript Security of Approximate Neural Networks against Power Side-channel Attack
Engineering Special Session AI-Enabled EDA for Chip Design
Networking timing-aware smart PG fill
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Engineering Poster Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Networking Boolean Reasoning Guided Ungrouping
Research Manuscript The Answer Is In-memory!? ... In the Memory? ... Memory? Find Out Here!
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Networking Boolean Reasoning Guided Ungrouping
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Networking Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
Engineering Presentation Accelerating SRAM Design Cycles With Additive AI Technology
Networking Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Research Manuscript Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
Research Manuscript Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Research Manuscript Graphs & Topology: The New Frontier in AI Modeling
Late Breaking Results Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
Engineering Presentation Analysis of Electrostatic Discharge (ESD) for 3DIC systems
B
Research Panel Navigating the Tides of Funding for Chips and System Design
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Networking Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Engineering Presentation Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Engineering Special Session A Look into the Future of Verification
Engineering Presentation Refresh your UVM Testbench with a Spritz of Python
Research Manuscript From Test to SLM Advanced Solutions
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Research Manuscript InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Research Manuscript Watts Up? AI/ML Enabled Advances in Power and Thermal Integrity
Research Panel Navigating the Tides of Funding for Chips and System Design
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Research Special Session Security Opportunities and Challenges for Disaggregated Architectures
Engineering Presentation Watt's Next: Low-Power Design and Verification Trends
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Networking Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Research Manuscript Uncertainty-Aware Energy Management for Wearable IoT Devices with Conformal Prediction
Research Manuscript Unleashing the Power of Accelerators: ASICs, FPGAs, and PIMs
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Special Session Incompatible: Test Quality and Fortuitous Detection
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript To Abstract or Not to Abstract the Storage Layer
Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Research Manuscript The Rise of AI, GPUs & Processors: The Next-Gen Architectures
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript The ‘Auto’ in Autonomous Systems
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Poster CTS with Machine Learning NDR
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
C
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Research Manuscript AdreamDCO: AI-Driven Robust and Efficient Design Automation for Digitally Controlled Oscillators
Research Manuscript EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript From Pixels to Chips: AI-Enhanced Layout & Mask Design
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript HoBBy: Hardening Unbalanced Branches against Control Flow Attacks on Intel SGX and AMD SEV
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Presentation Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript Identifying System-on-Chip Security Assets with Structure-Based Analysis
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Late Breaking Results Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU Computation
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript ACIM-QMM: Efficient Analog Computing-in-Memory Accelerator for QC-MDPC McEliece Cryptosystem
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-Oriented Components
Late Breaking Results Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization
Late Breaking Results Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Research Manuscript Navigating the Frontiers of Neural Networks
China
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge
Research Manuscript Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Special Session Advancing Quantum Computing for Tomorrow
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Engineering Poster Physical Aware RAM Sequential ATPG for IR Prevention
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript GPart: A GNN-Enabled Multilevel Graph Partitioner
China
China
China
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Research Manuscript H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
Research Manuscript LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Networking Dead Gate Elimination
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript Adventures in PCBs, Partitioning, and Legalization!
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Research Manuscript YAP: Yield Modeling and Simulation for Advanced Packaging
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Panel Navigating the Tides of Funding for Chips and System Design
Networking A DFT parallel test technology
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Research Manuscript Navigating 3D, Clock Trees, and Shared Learning
Networking Clock H-tree exploration in BSPDN
Engineering Presentation ML based PPA Push using XAI
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Networking OpenGC: An Open-Source Gain Cell Compiler
VP Technology
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Keynote Jason Cong
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Engineering Presentation Revolutionizing Digital ASIC Design through AI
China
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
D
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Engineering Special Session Keeping the Guard Up with Security across the Board
Research Special Session Large Language Model - the "Current Big Thing" in the Semiconductor World
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Engineering Presentation A Novel approach for workload based GPU datapath power optimization
Engineering Poster Audit Flow: A fast quality checker tool for early design convergence
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Networking Early Clock Network Jitter Estimation
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Follow the Logic: Advances in Logic Synthesis
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Research Manuscript ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Research Manuscript Smarter Systems: The Future of Hardware Efficiency in AI
Research Manuscript CXL-Interplay: Unraveling and Characterizing CXL Interference in Modern Computer Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Engineering Poster Design Quality Improvement Through Automation
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Networking Scalar Runahead
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Networking Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
E
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Research Manuscript Program, Debug, Accelerate: Software Innovations
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Presentation Software Development & AI Applications
Research Manuscript AI on Fire: Compute-in-Memory and Multiplication-Free Acceleration for the Next Era
Research Manuscript Innovative Techniques for Analog Circuit Simulation and Optimization
Engineering Presentation Enhancing Verification Efficiency with Garbage-Model Methodology
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Accelerating SRAM Design Cycles With Additive AI Technology
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
F
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Engineering Presentation Surviving Monte Carlo – Circuit Optimization Ideas
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
China
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Engineering Poster Chip reliability with antenna discharge path consideration
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Engineering Presentation AI-aided flow for digital verification of a multiprotocol SerDes PHY
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Manuscript Navigating the Frontiers of Neural Networks
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Engineering Presentation Arrival Pathways for Crossing the Chip-n-Package Routes
Networking Hierarchical Early Latchup Checking Flow
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Research Manuscript Exploring the Formal Frontier for Verification and Validation
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript Flattering Splatting: Gaussian Splatting, Video Processing, and Diffusion
Research Manuscript CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
G
Engineering Poster Maximizing IR sign-off coverage using Sigma-AV and its benefit on PPA
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Research Special Session Co-design of Quantum Processors for NISQ Applications
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Engineering Presentation IP Gold – New Digital Design Nuggets
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
China
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Presentation Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
Engineering Presentation Novel Clocks and Resets Architecture Model
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Presentation Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
Engineering Presentation Robust Verification for Complex Liberty IP
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Special Session A Look into the Future of Verification
Engineering Special Session A Look into the Future of Verification
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Research Manuscript The ‘Auto’ in Autonomous Systems
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Late Breaking Results Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Founder
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Analyst Presentation The Future of Mobility
Research Manuscript Security of Approximate Neural Networks against Power Side-channel Attack
China
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Networking Scalar Runahead
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Research Manuscript DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based Filtering
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript AI Meets Silicon: Transforming Hardware Design through AI-Driven Innovation
Engineering Presentation Securing Chiplet Integration: A System-in-Package Security Architecture.
Exhibitor Forum The Renaissance of EDA Startups
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Research Manuscript Watts Up? AI/ML Enabled Advances in Power and Thermal Integrity
Research Manuscript CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error Correction
Research Manuscript ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
Networking OpenGC: An Open-Source Gain Cell Compiler
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
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Engineering Presentation Guided Vectorless with Multi vector profiling for Memory PDN convergence
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Special Session Device-Aware Test: A Means to Attack Unmodeled Defects
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Engineering Presentation Identifying Soft-Resets in Design using RDC Tool Flow
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript All You Can Route Buffet
Research Manuscript Cost-Distance Steiner Trees for Timing-Constrained Global Routing
Networking Easy AI for STA teams
Engineering Presentation Novel Eddies in the Implementation Flow
Research Manuscript Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized Multicores
Research Manuscript Contention-Aware Forecasting of Energy Efficiency through Sequence-Based Models in Modern Heterogeneous Processors
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Research Manuscript We HAS to Have These HARDWARE ACCELERATOR SYSTEMS for Deep Learning!
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Transformers: Rise of the Optimized Large Language Models
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript Faster, Safer, Greener: AI-driven Evolution in Smart Edge
Networking HBM Timing Methodology with Liberty LVF
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Manuscript MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript DuQTTA: Dual Quantized Tensor-Train Adaptation with Decoupling Magnitude-Direction for Efficient Fine-Tuning of LLMs
Research Manuscript EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Late Breaking Results Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU Computation
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
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Research Special Session Quantum Computers and Their Role in Enabling Scientific Discovery
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Special Session Advanced Package Design & System Co-Optimization for Heterogeneous Integration
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
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Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Engineering Presentation Formal Property Verification on Xeon SoC owned IPs
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Networking Activity-Based Power Density Optimization
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Networking Hierarchical Early Latchup Checking Flow
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Networking Scalar Runahead
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Tutorial Quantum Computing Design Automation
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and Scheduling
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Networking Scalar Runahead
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript PairGraph: An Efficient Search-space-aware Accelerator for High-performance Concurrent Pairwise Queries
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Research Manuscript A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy Compression
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Optimizing Large Language Models: Speed, Size, and Smarts
Engineering Poster Design Quality Improvement Through Automation
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Engineering Presentation From Devices to Debug - Modeling Thoughtful Design Practices
Engineering Presentation MCP Induced Glitches
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
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Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
Engineering Poster Maximizing IR sign-off coverage using Sigma-AV and its benefit on PPA
Engineering Presentation Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
Engineering Presentation Robust Verification for Complex Liberty IP
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Research Special Session AAA: Advanced AI Accelerators
Research Manuscript FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Engineering Presentation Thermal Characteristic Analysis of Back-Side Power Delivery Network
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Engineering Poster Physical Aware RAM Sequential ATPG for IR Prevention
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Engineering Special Session SLM Is the New DFT – Are You Ready?
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
Research Manuscript All You Can Route Buffet
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Special Session Materials to Systems Design Automation for Advanced Chips
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript Flattering Splatting: Gaussian Splatting, Video Processing, and Diffusion
Networking I/O Power Grid Analysis Methodology
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript From Simulation to Threats, a Deep-dive into CPS and IoT Design
Networking Clock H-tree exploration in BSPDN
Research Manuscript InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Research Special Session Accelerated Quantum Supercomputing
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Networking Clock H-tree exploration in BSPDN
Engineering Presentation ML based PPA Push using XAI
Networking Clock H-tree exploration in BSPDN
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation Optimal Power Estimation Methodology for CXL Memory Controllers
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Networking Clock H-tree exploration in BSPDN
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Research Manuscript Intermittent Systems at Small Scale: Execution Model and Design Guidelines
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Everything About LLM and Transformer Accelerators
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Engineering Special Session A Look into the Future of Verification
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Research Manuscript Look Both Ways: New Directions in High-Level Synthesis and Approximate Computing
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Vice President & General Manager, Design Verification Technologies
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Hands-On Training Session Enabling Seamless Hybrid Cloud Transitions for EDA & Systems Design with Cadence True Hybrid Cloud
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Networking Early Clock Network Jitter Estimation
Research Manuscript Quantum Breakthroughs Creating Game-Changing Applications
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Engineering Poster Portfolio Re-characterization using AI
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript We HAS to Have These HARDWARE ACCELERATOR SYSTEMS for Deep Learning!
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Poster Portfolio Re-characterization using AI
Networking Boolean Reasoning Guided Ungrouping
Engineering Poster Portfolio Re-characterization using AI
Engineering Presentation Robust Verification for Complex Liberty IP
Engineering Presentation Energy Efficient I3C IP Subsystem for Low Power IoT
Engineering Presentation Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
Engineering Special Session Keeping the Guard Up with Security across the Board
Research Special Session Quantum-Resistant Security: PQC Readiness and Research Challenges
Engineering Presentation Identifying Soft-Resets in Design using RDC Tool Flow
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
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DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Networking Automating RTL generation using Agentic LLMs
Engineering Special Session A Look into the Future of Verification
Engineering Poster Chip reliability with antenna discharge path consideration
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Research Manuscript Skip the Bits!: Innovative Arithmetic, Architecture, Co-Design for AI
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Special Session Generative AI: A transformational technology for IC Design
Engineering Poster Chip reliability with antenna discharge path consideration
Engineering Presentation AACT: Automated Analog Coverage Tool for Mixed Signal Verification
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript Balancing Speed and Memory: Advancing LLM Acceleration
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Networking Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript A Post-Implementation Performance Prediction Method with HLS Optimization Directives
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Research Manuscript Asymmetric Predictive Testing for Aging in SRAMs
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Networking OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript LLM Uprising: Fast & Furious
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
Research Manuscript Spike It, See It, Say It: Next-Gen AI Processing
Research Manuscript Squeezing Placement from FPGAs, Macros, Down to the Cell Level
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Networking Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript Synthesis of CFET Cell Library Leveraging Backside Metal Routing
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Optimizing Large Language Models: Speed, Size, and Smarts
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
China
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Networking Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Research Manuscript Building Pillars of Quantum Circuits: Synthesis, Simulation & Compilation
Research Manuscript EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits
Tutorial Quantum Computing Design Automation
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript Intermittent Systems at Small Scale: Execution Model and Design Guidelines
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Research Manuscript DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosis
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript Synthesis of CFET Cell Library Leveraging Backside Metal Routing
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Research Manuscript Asymmetric Predictive Testing for Aging in SRAMs
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Networking HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Research Manuscript From Test to SLM Advanced Solutions
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript ALLMod: Exploring \underline{A}rea-Efficiency of \underline{L}UT-based \underline{L}arge Number \underline{Mod}ular Reduction via Hybrid Workloads
Research Manuscript ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum Devices
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Quantization
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Exhibitor Forum A Configurable ECAD Library Solution for All Users
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Research Manuscript DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge
Research Manuscript Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Networking OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Identifying System-on-Chip Security Assets with Structure-Based Analysis
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript Graphs & Topology: The New Frontier in AI Modeling
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
China
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Networking Boolean Reasoning Guided Ungrouping
Research Manuscript Quantum Breakthroughs Creating Game-Changing Applications
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Special Session Scalable Heterogenous Photonic Design Automation
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum Devices
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Networking HBM Timing Methodology with Liberty LVF
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
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Engineering Presentation AACT: Automated Analog Coverage Tool for Mixed Signal Verification
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Research Manuscript CXL-Interplay: Unraveling and Characterizing CXL Interference in Modern Computer Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript Navigating 3D, Clock Trees, and Shared Learning
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript AI Meets Silicon: Transforming Hardware Design through AI-Driven Innovation
Exhibitor Forum The Renaissance of EDA Startups
Research Special Session Multi-Scale Thermal-Mechanical Modeling of Advanced Chips
Research Manuscript Approximate SMT Counting Beyond Discrete Domains
Research Special Session Towards Secure Data Management using Multi-cryptographic Solutions
Networking Dead Gate Elimination
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Networking Boolean Reasoning Guided Ungrouping
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Special Session Quantum Threats, Disaggregated Architectures, and Cryptography Leakages
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Networking Early Clock Network Jitter Estimation
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
VP of Solutions Engineering for Helix IPLM
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Research Manuscript LLM Uprising: Fast & Furious
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
VP, Semiconductor Industry
Exhibitor Forum Engineering the Semiconductor Digital Thread
Engineering Presentation Taming Formal to define the Verification Quality
Engineering Special Session SLM Is the New DFT – Are You Ready?
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Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Late Breaking Results Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Engineering Presentation ML based PPA Push using XAI
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Research Manuscript Exploring the Unchartered: From Chiplets to Architecture and Validation
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript Transformers: Rise of the Optimized Large Language Models
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript Breaking & Securing the Future: Advances in System & Hardware Security
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Tutorial Quantum Computing Design Automation
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
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Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript LLM/DL Driven Analog Circuit Design and Analysis
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
Networking A DFT parallel test technology
Networking A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
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DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Networking timing-aware smart PG fill
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
IEEE TCVLSI Co-chair
Networking timing-aware smart PG fill
IEEE TCVLSI Chair
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Research Manuscript Mitigating Routability Problems in Complementary-FET-based VLSI Designs
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Research Manuscript FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Analyst Presentation Accelerator Package and System Design For The AI Era
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Networking Multiple Row Buffer DRAM
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Research Manuscript The Answer Is In-memory!? ... In the Memory? ... Memory? Find Out Here!
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Networking A DFT parallel test technology
Networking A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Research Manuscript Cost-Distance Steiner Trees for Timing-Constrained Global Routing
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript Look Both Ways: New Directions in High-Level Synthesis and Approximate Computing
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Exhibitor Forum Mastering Modern Data Management: Insights and Case Studies
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Research Special Session SambaNova SN40L: Unleashing Agentic AI with Dataflow
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript Adventures in PCBs, Partitioning, and Legalization!
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
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Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM Systems
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript All Quiet on the Processor Front: Next-Gen Processor Security and Enclave Innovations
Research Manuscript BPUFuzzer: Effective Fuzz Testing for Branching Transient Execution Vulnerabilities of RISC-V CPU
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
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Networking Beyond Verilog: Agents for Emerging HDLs
Research Manuscript New Frontiers in Microarchitectural and Physical Attacks and Defenses
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Engineering Poster Guided Physical Power Optimization of AI Silicon
Engineering Poster Recipe Explorer: Crafting the Missing PD Flow Layer
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Special Session Architecture and Design Approaches towards Large-scale AI Hardware Acceleration
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Presentation Custom IP Blocks – The Lego Blocks of Digital Design
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Presentation Robust Verification for Complex Liberty IP
Research Manuscript ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning
Networking Hierarchical Early Latchup Checking Flow
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Engineering Presentation AI and Chiplet/Multi-die: Verification Scalability and AI driven Automation
Research Manuscript ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Networking Beyond Verilog: Agents for Emerging HDLs
Engineering Presentation Verification Innovation: Shaping the Future of Design Validation
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Research Manuscript PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
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Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Engineering Presentation Formal and Static Verification: Stop Bugs Before They Think They're Invited
Research Special Session Advancing Quantum Computing for Tomorrow
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment
Engineering Presentation Enhancing verification throughput in random tests regression with a novel machine learning engine
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Research Special Session EDA for Heterogeneous Integration
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Engineering Presentation Back-end and System Considerations for Chiplets
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Engineering Presentation Guided Vectorless with Multi vector profiling for Memory PDN convergence
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Networking Dead Gate Elimination
Research Manuscript Storage Meets Computing Power for Advancing AI and Data Processing Efficiency
Engineering Presentation A Novel approach for workload based GPU datapath power optimization
Research Special Session AAA: Advanced AI Accelerators
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning
Research Manuscript CognitiveArm: Enabling Real-Time EEG-Controlled Prosthetic Arm Using Embodied Machine Learning
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
Research Manuscript Turbocharging Deep Learning Training: Efficiency Meets Innovation
Engineering Presentation AUTOLNKGEN: Automated Random Linker File Generation Framework for Heterogenous SoC Verification & Validation
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Research Manuscript Exploring the Formal Frontier for Verification and Validation
Engineering Poster Portfolio Re-characterization using AI
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Research Manuscript Approximate SMT Counting Beyond Discrete Domains
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Networking HBM Timing Methodology with Liberty LVF
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and Scheduling
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Research Manuscript AI Under Attack: Enhancing Privacy, Robustness, and Trust in ML Systems
Research Special Session Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Presentation MCP Induced Glitches
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Engineering Presentation Taming Formal to define the Verification Quality
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Special Session AI-Enabled EDA for Chip Design
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Presentation Accelerated SoC Level Android Home Screen Bring-up, System Software Development and Validation at Pre-Silicon with Advanced Hybrid Emulation Methodology
Networking Comprehensive solution for Optimizing and Accelerating Gate level simulation for complex SOCs
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Research Manuscript Back to the Future: Where Speed Meets Efficiency
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Research Manuscript Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Special Session Advanced Packaging: Promise and the Needs
Networking Automating RTL generation using Agentic LLMs
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
China
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript Squeezing Placement from FPGAs, Macros, Down to the Cell Level
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
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Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Tutorial Quantum Computing Design Automation
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript Innovative Techniques for Analog Circuit Simulation and Optimization
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Networking Scalar Runahead
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Engineering Presentation Novel Clocks and Resets Architecture Model
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Special Session On the Limitations of VLSI Structural Manufacturing Test and Future Directions
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
DAC Pavilion Panel Design, Develop, Dominate: The CHIPS Act's Role in Semiconductor Innovation
Hands-On Training Session Enhance Perforce/Synopsys VCS Workflows Using AWS and AWS FSx for NetApp ONTAP
Networking Boolean Reasoning Guided Ungrouping
Engineering Presentation AI-aided flow for digital verification of a multiprotocol SerDes PHY
Networking Boolean Reasoning Guided Ungrouping
Research Manuscript Follow the Logic: Advances in Logic Synthesis
Engineering Special Session AI-Enabled EDA for Chip Design
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Research Manuscript Pushing Quantum Computing Reality from Routing to Error Corrections and QML
Research Special Session Materials-Device-Systems Co-optimization using AI/ML
Research Special Session Enhancing Design Automation with AI and Quantum Algorithms for Chip Design
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Networking Automating RTL generation using Agentic LLMs
Senior Director
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Research Manuscript Ready, Set, Scale! AI's Journey from Edge to Cloud Optimization
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript Shaping Tomorrow: Co-Designing Emerging Technologies for Computing and Beyond
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Research Manuscript Right on Time, Built to Last: New Frontiers in Critical System Design
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
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Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Presentation Securing Chiplet Integration: A System-in-Package Security Architecture.
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Engineering Presentation Grid Resilience - Powering Solutions Design and Delivery for the Performance Promises
Networking OpenGC: An Open-Source Gain Cell Compiler
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Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Engineering Poster Portfolio Re-characterization using AI
Engineering Presentation Robust Verification for Complex Liberty IP
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Exhibitor Forum The Generative AI Revolution in Semiconductor Development
Networking Boolean Reasoning Guided Ungrouping
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Analyst Presentation View from Wall Street
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
W
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
China
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Late Breaking Results Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Manuscript Models and Hardware for Machine Learning and Beyond
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Tutorial Quantum Computing Design Automation
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Networking Scalar Runahead
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Special Session LLMs Meet Post-Silicon Test Engineering: A New Era
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
China
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Engineering Presentation Novel Clocks and Resets Architecture Model
Networking A DFT parallel test technology
Research Manuscript Leveraging the Memory Hierarchy for Emerging Applications and Hardware
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Manuscript GPart: A GNN-Enabled Multilevel Graph Partitioner
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Construction of DAG Models for Autonomous Systems
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Networking Scalar Runahead
Networking OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript The Unwritten Contract of Cloud-based Elastic Solid-State Drives
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosis
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript ALLMod: Exploring \underline{A}rea-Efficiency of \underline{L}UT-based \underline{L}arge Number \underline{Mod}ular Reduction via Hybrid Workloads
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Quantization
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Tutorial Quantum Computing Design Automation
Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Networking Scalar Runahead
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Networking OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript Scaling, Learning, and Parallelizing the Future of Verification and Synthesis
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Special Session Energy-Efficient On-Device AI Acceleration and More Enabled By 3D Integration
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
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Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Networking A DFT parallel test technology
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
China
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
China
Research Manuscript ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Research Manuscript AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Research Manuscript A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Networking HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Networking Scalar Runahead
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript A PulseWidth-IN-PulseWidth-Out Universal Nonlinear Processing Element for Time-Domain In-Memory Computing Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
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Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Networking OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
Research Manuscript Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis
Research Manuscript GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Research Manuscript Turbocharging Deep Learning Training: Efficiency Meets Innovation
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Research Manuscript Program, Debug, Accelerate: Software Innovations
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript The Unwritten Contract of Cloud-based Elastic Solid-State Drives
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Manuscript Hybrid Embedding Framework for Memory-Efficient Recommendation Systems
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript Smarter Compute, Faster Inference: Optimizing AI Systems on Edge
China
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
China
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Research Manuscript 3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs
Research Manuscript 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Research Manuscript PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems
Research Manuscript FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Research Manuscript Mitigating Routability Problems in Complementary-FET-based VLSI Designs
Engineering Presentation Enhancing Verification Efficiency with Garbage-Model Methodology
Research Manuscript MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Networking Scalar Runahead
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Manuscript E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Research Manuscript ML-Powered Logic Synthesis
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Research Manuscript A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Z
Networking Beyond Verilog: Agents for Emerging HDLs
Exhibitor Forum The Renaissance of EDA Startups
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Research Manuscript Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration
Research Manuscript MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Networking HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
Networking ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Networking A DFT parallel test technology
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript Breaking & Securing the Future: Advances in System & Hardware Security
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
China
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
China
Research Manuscript CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error Correction
Research Manuscript ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Networking HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
Networking ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript Breakthroughs in Timing Prediction, Analysis, and Optimization
Engineering Poster Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Networking A DFT parallel test technology
Networking A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript Smarter Compute, Faster Inference: Optimizing AI Systems on Edge
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Research Manuscript Faster, Safer, Greener: AI-driven Evolution in Smart Edge
Research Manuscript ML-Powered Logic Synthesis
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition
Research Manuscript Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems
Research Manuscript FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization
Research Manuscript FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUT
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs