Contributors
A
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Work-in-Progress Poster TEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric Prediction
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Work-in-Progress Poster Analytical Optimization for Robust and Efficient Analog IC Design Automation
Work-in-Progress Poster Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
Work-in-Progress Poster LightCROSS: A Secure and Memory Optimized Post-Quantum Digital Signature CROSS
Research Manuscript Security of Approximate Neural Networks against Power Side-channel Attack
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Engineering Special Session AI-Enabled EDA for Chip Design
Engineering Poster timing-aware smart PG fill
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Work-in-Progress Poster dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUs
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Engineering Poster Autonomous Physical Design: Accelerating ASIC Design using Machine Learning
Work-in-Progress Poster FARM: Fast Acceleration of Random forests via in-Memory processing
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Work-in-Progress Poster Non-Negative AdderNet (NNAN): Can We Make DNNs More Secure and Efficient Without Multiplication?
Work-in-Progress Poster SafeSSD: Treeless SSD Protection by Leveraging Physical Address as Version Number
Research Special Session Scalable Heterogenous Photonic Systems with Design Automation
Research Manuscript Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells
Work-in-Progress Poster A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Work-in-Progress Poster CLEAR-HD: Computationally Light and Effective Unlearning for Hyperdimensional Computing
Engineering Poster A new methodology to generate a multitude of SoC configurations quickly
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Engineering Poster Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
Work-in-Progress Poster Non-Negative AdderNet (NNAN): Can We Make DNNs More Secure and Efficient Without Multiplication?
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Work-in-Progress Poster The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration
Work-in-Progress Poster Heterogeneous Approximate Multiplications: A New Frontier for Practical DNNs
Work-in-Progress Poster Accelerating device level synthesis of binarized convolutional neural networks
Work-in-Progress Poster The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration
Engineering Poster ESD EDA Verification Flow Applied to Smart Power IC's
Work-in-Progress Poster Dyna-Optics: Architecting a Channel-Adaptive DNN Near-Sensor Optical Accelerator for Dynamic Inference
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Engineering Poster Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
Engineering Presentation Accelerating SRAM Design Cycles With Additive AI Technology
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Work-in-Progress Poster The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration
Work-in-Progress Poster CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Work-in-Progress Poster A PCA and KDE Based Approach for Statistical CMOS Compact Model Parameter Generation
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Work-in-Progress Poster CLEAR-HD: Computationally Light and Effective Unlearning for Hyperdimensional Computing
Work-in-Progress Poster Design-Aware Multi-Armed Bandit Approach for Automated Design Verification
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Engineering Poster Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
Engineering Presentation Accelerating SRAM Design Cycles With Additive AI Technology
Work-in-Progress Poster Deep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applications
Senior Vice President and General Manager, Infrastructure Line of Business
Work-in-Progress Poster TiLeR: Hardware-In-The-Loop Mitigation of Software Timing Side-Channel Vulnerabilities
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Research Manuscript Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
Research Manuscript Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Research Manuscript Graphs & Topology: The New Frontier in AI Modeling
Late Breaking Results Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
Engineering Presentation Analysis of Electrostatic Discharge (ESD) for 3DIC systems
B
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Work-in-Progress Poster Directed on-the-fly Validation of Hierarchical Cache Coherence Protocols
Work-in-Progress Poster Transistor Placement Routability Prediction for Standard Cell Design
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Work-in-Progress Poster Out of The Box Techniques for Data Path Verification
Research Panel Navigating the Tides of Funding for Chips and System Design
Work-in-Progress Poster Energy-Efficient, Real-Time Robotic Path Planning through FPGA Acceleration
Work-in-Progress Poster MTrace : Trusted logging using ARM DWT on embedded devices
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Poster CDC-RDC Inter-operable collateral Standardization
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Engineering Poster Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Engineering Presentation Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Engineering Poster Validation journey of SOC High Speed Interfaces: From sim to real device
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Engineering Special Session A Look into the Future of Verification
Engineering Presentation Refresh your UVM Testbench with a Spritz of Python
Work-in-Progress Poster Design-Aware Multi-Armed Bandit Approach for Automated Design Verification
Work-in-Progress Poster Directed on-the-fly Validation of Hierarchical Cache Coherence Protocols
Work-in-Progress Poster MERINDA: Model Recovery in FPGA based Dynamic Architecture
Research Manuscript From Test to SLM Advanced Solutions
Research Manuscript Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Engineering Poster HSTAF: Hierarchical Static Timing Analysis Flow
Engineering Poster Automation of Shmoo Engine based Pre-Si BDI Testing
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Work-in-Progress Poster SwiftMax: Reducing Training Time for Learnable Softmax Alternative in Customized Acceleration
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Work-in-Progress Poster Transistor Placement Routability Prediction for Standard Cell Design
Research Manuscript LLM/DL Driven Analog Circuit Design and Analysis
Research Manuscript InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Research Manuscript Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Research Manuscript Watts Up? AI/ML Enabled Advances in Power and Thermal Integrity
Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Poster Improving Digital Design performance and area using DSO.ai
Engineering Poster Solving Configuration Challenge with SVRAND Verification Flow
Work-in-Progress Poster Towards Accurate, Real-Time, and Energy-Efficient Attention Monitoring
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Work-in-Progress Poster FARM: Fast Acceleration of Random forests via in-Memory processing
Research Special Session Security Opportunities and Challenges for Disaggregated Architectures
Engineering Poster Improving Digital Design performance and area using DSO.ai
Engineering Presentation Watt's Next: Low-Power Design and Verification Trends
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Engineering Poster Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Research Manuscript Uncertainty-Aware Energy Management for Wearable IoT Devices with Conformal Prediction
Research Manuscript Unleashing the Power of Accelerators: ASICs, FPGAs, and PIMs
Work-in-Progress Poster AdaMAP: Adaptive Hardware Mapping for Model Compression using Low-Rank Decomposition
Work-in-Progress Poster Extending RISC-V based GPGPU for fast execution of regular data-intensive kernels
Research Manuscript Skip the Bits!: Innovative Arithmetic, Architecture, Co-Design for AI
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Engineering Poster Generative AI for improving the productivity in Analog & Mixed Signal design flows
Engineering Poster Method & Apparatus to Migrate Design Repositories into Cloud
Work-in-Progress Poster Quantum Properties Trojans (QuPTs) for Attacking QNNs
Engineering Poster A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
Engineering Poster ESD EDA Verification Flow Applied to Smart Power IC's
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Engineering Poster A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Research Special Session Incompatible: Test Quality and Fortuitous Detection
Senior Fellow
Keynote Enabling the AI Revolution
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster Transistor Placement Routability Prediction for Standard Cell Design
Research Manuscript To Abstract or Not to Abstract the Storage Layer
Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Work-in-Progress Poster The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Engineering Poster A new methodology to generate a multitude of SoC configurations quickly
Work-in-Progress Poster ROPE-MLA: Row-Access Optimized Processing Element Machine Learning Accelerator
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript The ‘Auto’ in Autonomous Systems
Engineering Poster Real-time Process Margin-based Layout Optimization
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Engineering Special Session SLM Is the New DFT – Are You Ready?
Work-in-Progress Poster FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
Engineering Poster CTS with Machine Learning NDR
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
C
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript Back to the Future: Where Speed Meets Efficiency
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Work-in-Progress Poster Dynamic FPGA Acceleration for Cloud Workloads: A HLS-based JIT Compilation Approach
Research Special Session Accelerated Quantum Supercomputing
Research Manuscript AdreamDCO: AI-Driven Robust and Efficient Design Automation for Digitally Controlled Oscillators
Research Manuscript EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript From Pixels to Chips: AI-Enhanced Layout & Mask Design
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript HoBBy: Hardening Unbalanced Branches against Control Flow Attacks on Intel SGX and AMD SEV
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Research Manuscript SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models
Work-in-Progress Poster ScaleX: A Scalable and Flexible Architecture for Efficient GNN Inference
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Presentation Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Work-in-Progress Poster The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration
Research Manuscript Identifying System-on-Chip Security Assets with Structure-Based Analysis
Work-in-Progress Poster Directed on-the-fly Validation of Hierarchical Cache Coherence Protocols
Research Manuscript Circuit Breakers: Secrets Unleashed!
Research Manuscript POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Work-in-Progress Poster TiLeR: Hardware-In-The-Loop Mitigation of Software Timing Side-Channel Vulnerabilities
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Work-in-Progress Poster LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
Engineering Poster Single Corner Mixed Voltage Functional Noise Analysis
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Late Breaking Results Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU Computation
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Work-in-Progress Poster Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript ACIM-QMM: Efficient Analog Computing-in-Memory Accelerator for QC-MDPC McEliece Cryptosystem
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Work-in-Progress Poster Analytical Warpage-aware Multi-die Floorplanning for Advanced Package Designs
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-Oriented Components
Late Breaking Results Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization
Late Breaking Results Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Work-in-Progress Poster Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Engineering Poster SigmaAV: High Global and Local Noise Coverage Solution for Power Integrity Signoff
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Research Manuscript Navigating the Frontiers of Neural Networks
China
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
VP of Mission Systems
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Engineering Poster An Efficient Methodology of Analyzing Rush Current in Power Gated Design
Engineering Poster timing-aware smart PG fill
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge
Research Manuscript Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Work-in-Progress Poster Edge Continual Learning with Mixed-Signal Gaussian Mixture-based Bayesian Neural Networks
Research Special Session Advancing Quantum Computing for Tomorrow
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Work-in-Progress Poster Blaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum Circuits
Work-in-Progress Poster Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
Engineering Poster Physical Aware RAM Sequential ATPG for IR Prevention
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Poster A X-mask Chip Fast Binning Technology
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript GPart: A GNN-Enabled Multilevel Graph Partitioner
Work-in-Progress Poster Analytical Warpage-aware Multi-die Floorplanning for Advanced Package Designs
China
Work-in-Progress Poster IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Work-in-Progress Poster Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
China
China
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Research Manuscript H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
Research Manuscript LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Work-in-Progress Poster A Novel Multi-Node-Upset Recoverability Verification Method with Generalized Model for Radiation-Hardened Latches
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Work-in-Progress Poster Dead Gate Elimination
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Work-in-Progress Poster Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript Adventures in PCBs, Partitioning, and Legalization!
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Research Manuscript YAP: Yield Modeling and Simulation for Advanced Packaging
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Pushing Quantum Computing Reality from Routing to Error Corrections and QML
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Panel Navigating the Tides of Funding for Chips and System Design
Research Manuscript Smarter Systems: The Future of Hardware Efficiency in AI
Engineering Poster A DFT parallel test technology
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster FAxC: Exploiting Feature Approximation for Privacy Preservation in Human Activity Recognition
Work-in-Progress Poster CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Engineering Special Session A Look into the Future of Verification
Research Manuscript Navigating 3D, Clock Trees, and Shared Learning
Work-in-Progress Poster Multiple Row Buffer DRAM
Engineering Poster Pre-Validation Tool: Minimizing Errors, Maximizing Efficiency
Engineering Poster Clock H-tree exploration in BSPDN
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Engineering Presentation ML based PPA Push using XAI
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Work-in-Progress Poster Pacemaker: Energy-Efficient Speculative Scheduling Window Resizing without Performance Impact
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Work-in-Progress Poster CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Engineering Poster Autonomous Physical Design: Accelerating ASIC Design using Machine Learning
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
VP Technology
Work-in-Progress Poster CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Volegnau Chair for Engineering Excellence Professor United States of America
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Work-in-Progress Poster CPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware Vulnerability
China
Work-in-Progress Poster Ordering-Centric: A Scalable and Exact Method for Scheduling with Resource Constraints
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Work-in-Progress Poster CD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator Impurities
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
D
Engineering Poster A new methodology to generate a multitude of SoC configurations quickly
DAC Pavilion Panel Design, Develop, Dominate: The CHIPS Act's Role in Semiconductor Innovation
Work-in-Progress Poster IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
Research Manuscript Breaking Barriers: Compute-in-Memory for Transformer Acceleration
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Work-in-Progress Poster A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Work-in-Progress Poster SOFTONIC: A Photonic Design Approach to SoftMax Activation for High-Speed Analog AI Acceleration
Engineering Poster Optimizing Power Integrity with Smart PDN Framework
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Research Special Session Quantum Threats, Disaggregated Architectures, and Cryptography Leakages
Engineering Special Session Keeping the Guard Up with Security across the Board
Research Special Session Large Language Model - the "Current Big Thing" in the Semiconductor World
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Engineering Presentation A Novel approach for workload based GPU datapath power optimization
Work-in-Progress Poster SOFTONIC: A Photonic Design Approach to SoftMax Activation for High-Speed Analog AI Acceleration
Engineering Poster Audit Flow: A fast quality checker tool for early design convergence
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Engineering Poster Early Clock Network Jitter Estimation
Engineering Poster Autonomous Physical Design: Accelerating ASIC Design using Machine Learning
Engineering Poster HSTAF: Hierarchical Static Timing Analysis Flow
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Work-in-Progress Poster Edge Continual Learning with Mixed-Signal Gaussian Mixture-based Bayesian Neural Networks
Work-in-Progress Poster ROPE-MLA: Row-Access Optimized Processing Element Machine Learning Accelerator
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Follow the Logic: Advances in Logic Synthesis
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Work-in-Progress Poster CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Research Manuscript ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Work-in-Progress Poster ReVEAL: Reverse Engineering of Multiplier Architectures via Graph Learning for Computer Algebra Verification
Research Manuscript Smarter Systems: The Future of Hardware Efficiency in AI
Research Manuscript CXL-Interplay: Unraveling and Characterizing CXL Interference in Modern Computer Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Work-in-Progress Poster LPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT Algorithm
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Work-in-Progress Poster Energy-Efficient, Real-Time Robotic Path Planning through FPGA Acceleration
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Work-in-Progress Poster Multiple Row Buffer DRAM
Engineering Poster Design Quality Improvement Through Automation
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Research Manuscript From Simulation to Threats, a Deep-dive into CPS and IoT Design
Work-in-Progress Poster Accelerating device level synthesis of binarized convolutional neural networks
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript To Tackle Cost-Skew Tradeoff: An Adaptive Learning Approach for Hub Node Selection
Work-in-Progress Poster Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning Framework
Work-in-Progress Poster A PCA and KDE Based Approach for Statistical CMOS Compact Model Parameter Generation
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Work-in-Progress Poster Accelerating device level synthesis of binarized convolutional neural networks
Work-in-Progress Poster Combining Physics-Informed and Data-Driven Learning for Efficient Modeling of Memristive Devices
Research Manuscript The Answer Is In-memory!? ... In the Memory? ... Memory? Find Out Here!
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Work-in-Progress Poster ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster Scalar Runahead
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Engineering Poster A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
Engineering Poster Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Poster Circuit Design and Optimization Methodology ensuring Area optimized, Robust and Reliable I/O Interface for Wide Range of Application use
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
E
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Research Manuscript An Energy-Efficient Kalman Filter Architecture with Tunable Accuracy for Brain-Computer Interfaces
Research Manuscript The Rise of AI, GPUs & Processors: The Next-Gen Architectures
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Presentation Software Development & AI Applications
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Research Manuscript AI on Fire: Compute-in-Memory and Multiplication-Free Acceleration for the Next Era
Research Manuscript Innovative Techniques for Analog Circuit Simulation and Optimization
Engineering Presentation Enhancing Verification Efficiency with Garbage-Model Methodology
Work-in-Progress Poster Edge Continual Learning with Mixed-Signal Gaussian Mixture-based Bayesian Neural Networks
Engineering Poster Building a Parallel Simulation Kernel for Faster & Better Virtual Platforms
Engineering Presentation Software Development & AI Applications
Engineering Presentation Accelerating SRAM Design Cycles With Additive AI Technology
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Work-in-Progress Poster Efficient Runtime Management of Crossbars for Path-based In-Memory Computing
F
Research Manuscript DARIS: An Oversubscribed Spatio-Temporal Scheduler for Real-Time DNN Inference on GPUs
Research Manuscript Unleashing the Power of Accelerators: ASICs, FPGAs, and PIMs
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Work-in-Progress Poster A PCA and KDE Based Approach for Statistical CMOS Compact Model Parameter Generation
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Research Manuscript MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Work-in-Progress Poster Crosstalk-Aware Mapping for Optical Neural Networks
Engineering Presentation Surviving Monte Carlo – Circuit Optimization Ideas
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
DAC Pavilion Panel Design, Develop, Dominate: The CHIPS Act's Role in Semiconductor Innovation
Work-in-Progress Poster EvoSolo: Evolutionary Sequence Optimization for Logic Synthesis with Cascaded PPO
Research Manuscript Generalizable Lithographic Hotspot Detection Using Asynchronous Meta-Learning with Only One Shot
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
China
Work-in-Progress Poster Ordering-Centric: A Scalable and Exact Method for Scheduling with Resource Constraints
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Work-in-Progress Poster dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUs
Engineering Poster Chip reliability with antenna discharge path consideration
Work-in-Progress Poster Design-Aware Multi-Armed Bandit Approach for Automated Design Verification
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Engineering Poster Real-time Process Margin-based Layout Optimization
Engineering Presentation AI-aided flow for digital verification of a multiprotocol SerDes PHY
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Manuscript Navigating the Frontiers of Neural Networks
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Engineering Presentation Arrival Pathways for Crossing the Chip-n-Package Routes
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Engineering Poster Hierarchical Early Latchup Checking Flow
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Research Manuscript Exploring the Formal Frontier for Verification and Validation
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
Work-in-Progress Poster ROPE-MLA: Row-Access Optimized Processing Element Machine Learning Accelerator
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Research Manuscript EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
Work-in-Progress Poster HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
Research Manuscript Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
Work-in-Progress Poster Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript Flattering Splatting: Gaussian Splatting, Video Processing, and Diffusion
Work-in-Progress Poster Transistor Placement Routability Prediction for Standard Cell Design
Research Manuscript CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
G
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Engineering Poster Maximizing IR sign-off coverage using Sigma-AV and its benefit on PPA
Engineering Poster Activity-Based Power Density Optimization
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Research Special Session Co-design of Quantum Processors for NISQ Applications
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
China
Work-in-Progress Poster Ordering-Centric: A Scalable and Exact Method for Scheduling with Resource Constraints
Engineering Poster IR-Aware Timing Analysis using Accurate DvD-PWL Flow for Advanced Technology Nodes
Engineering Poster Silicon Lifecycle Management in Automotive Design
Work-in-Progress Poster SynAlign: Annotating HDLs with Synthesis Results
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Presentation Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
Engineering Presentation Novel Clocks and Resets Architecture Model
Work-in-Progress Poster Leveraging Artificial Neural Networks for Accurate and Efficient Glitch Propagation Modeling
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Poster CDC-RDC Inter-operable collateral Standardization
Engineering Poster Enhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros/IP and Standard Cell Libraries
Engineering Presentation Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
Engineering Presentation Robust Verification for Complex Liberty IP
Research Manuscript Look Both Ways: New Directions in High-Level Synthesis and Approximate Computing
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Senior Director of Product Management
Hands-On Training Session Enhance Perforce/Synopsys VCS Workflows Using AWS and AWS FSx for NetApp ONTAP
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Special Session A Look into the Future of Verification
Engineering Special Session A Look into the Future of Verification
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Research Manuscript The ‘Auto’ in Autonomous Systems
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Late Breaking Results Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Founder
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Analyst Presentation The Future of Mobility
Work-in-Progress Poster CarbonEDA: Carbon-Aware Electronic Design Automation for Integrated Circuits
Research Manuscript Security of Approximate Neural Networks against Power Side-channel Attack
China
Research Manuscript Right on Time, Built to Last: New Frontiers in Critical System Design
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster Scalar Runahead
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Research Manuscript DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based Filtering
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript AI Meets Silicon: Transforming Hardware Design through AI-Driven Innovation
Engineering Presentation Securing Chiplet Integration: A System-in-Package Security Architecture.
Exhibitor Forum The Renaissance of EDA Startups
Engineering Poster PPA Friendly Custom Repeater Tree Insertion for High-Speed Designs
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Research Manuscript Watts Up? AI/ML Enabled Advances in Power and Thermal Integrity
Research Manuscript CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error Correction
Research Manuscript ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
Research Manuscript MemSeer: Leveraging Memory Failure Distinctions and Multi-Grained Prediction in Ultra-Scale Heterogeneous X86/ARM Clusters
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
Work-in-Progress Poster HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
Research Manuscript Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
Work-in-Progress Poster Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Research Manuscript Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Vice President & GM
TechTalk Unlocking the Power of AI in EDA
Work-in-Progress Poster MERINDA: Model Recovery in FPGA based Dynamic Architecture
Research Manuscript Asymmetric Predictive Testing for Aging in SRAMs
Research Manuscript CREST-CiM: Cross-Coupling-Enhanced Differential STT-MRAM for Robust Computing-in-Memory in Binary Neural Networks
Research Special Session Materials to Systems Design Automation for Advanced Chips
Engineering Poster Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
H
Engineering Presentation Guided Vectorless with Multi vector profiling for Memory PDN convergence
Work-in-Progress Poster Towards Accurate, Real-Time, and Energy-Efficient Attention Monitoring
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Special Session Device-Aware Test: A Means to Attack Unmodeled Defects
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Work-in-Progress Poster A Novel Standard Cell Structure and Physical Design Methodology to Enhance Routability
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Engineering Presentation Identifying Soft-Resets in Design using RDC Tool Flow
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Work-in-Progress Poster MetaGuard: Transforming Run-Time Hardware Trojan Detection using Meta Reinforcement Learning
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Engineering Special Session AI-Enabled EDA for Chip Design
Research Manuscript All You Can Route Buffet
Research Manuscript Cost-Distance Steiner Trees for Timing-Constrained Global Routing
Engineering Poster Easy AI for STA teams
Engineering Presentation Novel Eddies in the Implementation Flow
Research Manuscript Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized Multicores
Research Manuscript Contention-Aware Forecasting of Energy Efficiency through Sequence-Based Models in Modern Heterogeneous Processors
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Research Manuscript We HAS to Have These HARDWARE ACCELERATOR SYSTEMS for Deep Learning!
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Co-Executive Director
Research Manuscript 333-eDRAM - 3T Embedded DRAM Leveraging Monolithic 3D Integration of 3 Transistor Types: IGZO, Carbon Nanotube and Silicon FETs
Work-in-Progress Poster CarbonEDA: Carbon-Aware Electronic Design Automation for Integrated Circuits
Work-in-Progress Poster Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems
Work-in-Progress Poster Place-and-Route for Photonic Integrated Circuits using Industry-Standard EDA Tools
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Work-in-Progress Poster Bank-Split PIM: Enabling Concurrent PIM and Memory Operations for LLM Inference in Heterogeneous Systems
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Work-in-Progress Poster FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
Research Manuscript PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
Work-in-Progress Poster SafeSSD: Treeless SSD Protection by Leveraging Physical Address as Version Number
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Transformers: Rise of the Optimized Large Language Models
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Research Manuscript Faster, Safer, Greener: AI-driven Evolution in Smart Edge
Engineering Poster HBM Timing Methodology with Liberty LVF
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Work-in-Progress Poster CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Work-in-Progress Poster MemSearch: An Efficient Memristive In-memory Search Engine with Configurable Similarity Measures
Research Panel Navigating the Tides of Funding for Chips and System Design
Work-in-Progress Poster PipeSpec: Breaking Stage Dependencies in Hierarchical LLM Decoding
Work-in-Progress Poster Panther: A PIM-based Blockchain Database System Supporting Efficient Verifiable Queries
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Work-in-Progress Poster Blaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum Circuits
Research Manuscript Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation
Research Manuscript Scaling, Learning, and Parallelizing the Future of Verification and Synthesis
Research Manuscript MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript DuQTTA: Dual Quantized Tensor-Train Adaptation with Decoupling Magnitude-Direction for Efficient Fine-Tuning of LLMs
Research Manuscript EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Work-in-Progress Poster PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Research Manuscript SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model Training
Research Manuscript The Rise of AI, GPUs & Processors: The Next-Gen Architectures
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Late Breaking Results Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU Computation
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Work-in-Progress Poster LPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT Algorithm
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Work-in-Progress Poster OT-CRL: Online Tuning of DRAM Controllers Using Continual Reinforcement Learning
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster Fast random walk through reduction of absorbing Markov chain
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Research Special Session Scaling the Quantum EDA Toolchain with Machine Learning
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Special Session Advanced Package Design & System Co-Optimization for Heterogeneous Integration
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Presentation Formal signoff for Cross-Module Design logic: A novel approach to manage formal scope in increasingly complex systems
Work-in-Progress Poster Out of The Box Techniques for Data Path Verification
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
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Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Work-in-Progress Poster Towards Accurate, Real-Time, and Energy-Efficient Attention Monitoring
Work-in-Progress Poster Early Mismatch Detection in Analog Layout Using PLS Netlist
Engineering Presentation High Figure of Merit Polyphase Decimation Core IP
Engineering Poster Optimizing Power Integrity with Smart PDN Framework
Engineering Poster Real-time Process Margin-based Layout Optimization
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Engineering Presentation Formal Property Verification on Xeon SoC owned IPs
Work-in-Progress Poster MTrace : Trusted logging using ARM DWT on embedded devices
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Work-in-Progress Poster Heterogeneous Approximate Multiplications: A New Frontier for Practical DNNs
Engineering Poster Activity-Based Power Density Optimization
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Work-in-Progress Poster Computing-In-Memory Dataflow for Minimal Buffer Traffic
Research Manuscript Shaping Tomorrow: Co-Designing Emerging Technologies for Computing and Beyond
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Work-in-Progress Poster Pacemaker: Energy-Efficient Speculative Scheduling Window Resizing without Performance Impact
Work-in-Progress Poster Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Engineering Poster Pre-Validation Tool: Minimizing Errors, Maximizing Efficiency
Engineering Poster Hierarchical Early Latchup Checking Flow
Work-in-Progress Poster Efficient Runtime Management of Crossbars for Path-based In-Memory Computing
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Research Manuscript GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Work-in-Progress Poster PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Work-in-Progress Poster SOFTONIC: A Photonic Design Approach to SoftMax Activation for High-Speed Analog AI Acceleration
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript From Pixels to Chips: AI-Enhanced Layout & Mask Design
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Work-in-Progress Poster Scalar Runahead
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Tutorial Quantum Computing Design Automation
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and Scheduling
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Work-in-Progress Poster Scalar Runahead
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript PairGraph: An Efficient Search-space-aware Accelerator for High-performance Concurrent Pairwise Queries
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Research Manuscript Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
Work-in-Progress Poster Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Research Manuscript A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy Compression
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Work-in-Progress Poster PaGO: Pareto-Assisted Goal Optimization for Analog Circuit Sizing
Research Manuscript Optimizing Large Language Models: Speed, Size, and Smarts
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Engineering Poster Design Quality Improvement Through Automation
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Engineering Presentation Complete Your Power and Thermal Envelopes with Security and Predictability
Engineering Poster Congestion Free, Power Domain Aware Signal Multiplexing
Engineering Presentation MCP Induced Glitches
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
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Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
Engineering Poster Maximizing IR sign-off coverage using Sigma-AV and its benefit on PPA
Engineering Presentation Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
Engineering Presentation Robust Verification for Complex Liberty IP
DAC Pavilion Panel Design, Develop, Dominate: The CHIPS Act's Role in Semiconductor Innovation
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Poster Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Work-in-Progress Poster AI-enabled Efficient Extraction of Entire Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Research Special Session AAA: Advanced AI Accelerators
Work-in-Progress Poster AdaMAP: Adaptive Hardware Mapping for Model Compression using Low-Rank Decomposition
Research Manuscript FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Engineering Poster Physical Aware RAM Sequential ATPG for IR Prevention
Engineering Poster Solving Configuration Challenge with SVRAND Verification Flow
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Work-in-Progress Poster Genesis: A Spiking Neuromorphic Accelerator With On-chip Continual Learning
Engineering Special Session A Look into the Future of Verification
Work-in-Progress Poster LightCROSS: A Secure and Memory Optimized Post-Quantum Digital Signature CROSS
Engineering Special Session SLM Is the New DFT – Are You Ready?
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Engineering Poster Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
Engineering Poster Accurate Memory IR Sign-Off at Lower Tech nodes
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Research Manuscript All You Can Route Buffet
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Work-in-Progress Poster CD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator Impurities
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
Work-in-Progress Poster Towards Accurate, Real-Time, and Energy-Efficient Attention Monitoring
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript Flattering Splatting: Gaussian Splatting, Video Processing, and Diffusion
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Engineering Poster I/O Power Grid Analysis Methodology
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Research Manuscript From Simulation to Threats, a Deep-dive into CPS and IoT Design
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Engineering Poster Clock H-tree exploration in BSPDN
Work-in-Progress Poster POG: Parameter Optimization using Graph Neural Networks on Reinforcement Learning
Work-in-Progress Poster Self-Motivated Agents for Analog Circuit Optimization via Intrinsic Reward
Research Manuscript InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Engineering Poster Clock H-tree exploration in BSPDN
Engineering Presentation ML based PPA Push using XAI
Engineering Poster Clock H-tree exploration in BSPDN
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation Optimal Power Estimation Methodology for CXL Memory Controllers
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Work-in-Progress Poster FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Work-in-Progress Poster FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
Research Manuscript Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells
Late Breaking Results Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery
Work-in-Progress Poster Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Engineering Poster Clock H-tree exploration in BSPDN
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Research Manuscript Intermittent Systems at Small Scale: Execution Model and Design Guidelines
Research Manuscript Program, Debug, Accelerate: Software Innovations
Work-in-Progress Poster Addressing Sequential Constraints in Zoned Storage with Collective Log-Structured File System
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Everything About LLM and Transformer Accelerators
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Work-in-Progress Poster LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Vice President & General Manager, Design Verification Technologies
Engineering Poster Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Work-in-Progress Poster Panther: A PIM-based Blockchain Database System Supporting Efficient Verifiable Queries
Hands-On Training Session Enabling Seamless Hybrid Cloud Transitions for EDA & Systems Design with Cadence True Hybrid Cloud
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Engineering Poster Early Clock Network Jitter Estimation
Research Manuscript Quantum Breakthroughs Creating Game-Changing Applications
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Work-in-Progress Poster PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Engineering Poster Portfolio Re-characterization using AI
Work-in-Progress Poster Genesis: A Spiking Neuromorphic Accelerator With On-chip Continual Learning
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript We HAS to Have These HARDWARE ACCELERATOR SYSTEMS for Deep Learning!
Ancillary Meeting Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
Engineering Poster Portfolio Re-characterization using AI
Engineering Poster Optimizing Power Integrity with Smart PDN Framework
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Engineering Poster Portfolio Re-characterization using AI
Engineering Presentation Robust Verification for Complex Liberty IP
Engineering Poster Silicon Lifecycle Management in Automotive Design
Work-in-Progress Poster Early Mismatch Detection in Analog Layout Using PLS Netlist
Engineering Poster Activity-Based Power Density Optimization
Engineering Poster Activity-Based Power Density Optimization
Work-in-Progress Poster AdaMAP: Adaptive Hardware Mapping for Model Compression using Low-Rank Decomposition
Engineering Poster Design for Time Interleaving of Data using Sub-sampling Clocks
Engineering Presentation Energy Efficient I3C IP Subsystem for Low Power IoT
Engineering Presentation Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
Engineering Special Session Keeping the Guard Up with Security across the Board
Research Special Session Quantum-Resistant Security: PQC Readiness and Research Challenges
Research Manuscript Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Work-in-Progress Poster LightCROSS: A Secure and Memory Optimized Post-Quantum Digital Signature CROSS
Engineering Presentation Identifying Soft-Resets in Design using RDC Tool Flow
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Engineering Poster Single Corner Mixed Voltage Functional Noise Analysis
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
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DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Work-in-Progress Poster Automating RTL generation using Agentic LLMs
Engineering Poster Chip reliability with antenna discharge path consideration
Work-in-Progress Poster Blaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum Circuits
Engineering Poster Real-time Process Margin-based Layout Optimization
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Work-in-Progress Poster Addressing Sequential Constraints in Zoned Storage with Collective Log-Structured File System
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Engineering Presentation An engineering approach to high performance scannable flip flops embedding functional logics
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Research Manuscript Skip the Bits!: Innovative Arithmetic, Architecture, Co-Design for AI
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster MTrace : Trusted logging using ARM DWT on embedded devices
Work-in-Progress Poster A Novel Standard Cell Structure and Physical Design Methodology to Enhance Routability
Engineering Presentation Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Work-in-Progress Poster Fast random walk through reduction of absorbing Markov chain
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Special Session Generative AI: A transformational technology for IC Design
Engineering Poster Chip reliability with antenna discharge path consideration
Engineering Presentation AACT: Automated Analog Coverage Tool for Mixed Signal Verification
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Special Session AI-Enabled EDA for Chip Design
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Research Manuscript Balancing Speed and Memory: Advancing LLM Acceleration
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Research Manuscript A Post-Implementation Performance Prediction Method with HLS Optimization Directives
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Research Manuscript Asymmetric Predictive Testing for Aging in SRAMs
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Work-in-Progress Poster Dynamic FPGA Acceleration for Cloud Workloads: A HLS-based JIT Compilation Approach
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Work-in-Progress Poster SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
Work-in-Progress Poster Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Research Manuscript LLM Uprising: Fast & Furious
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
Work-in-Progress Poster LPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT Algorithm
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript Squeezing Placement from FPGAs, Macros, Down to the Cell Level
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
Research Manuscript PUFiM: A Robust and Efficient FeFET-Based Security Solution Merging Physical Unclonable Function with Compute-in-Memory for Edge AI
Research Manuscript Spike It, See It, Say It: Next-Gen AI Processing
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript Synthesis of CFET Cell Library Leveraging Backside Metal Routing
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Optimizing Large Language Models: Speed, Size, and Smarts
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Work-in-Progress Poster LUT-MM: An Efficient Lookup Table-Based Approach for Modular Multiplication
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
China
Research Manuscript EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Construction of DAG Models for Autonomous Systems
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Work-in-Progress Poster Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Research Manuscript Building Pillars of Quantum Circuits: Synthesis, Simulation & Compilation
Research Manuscript EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits
Tutorial Quantum Computing Design Automation
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Work-in-Progress Poster LLM-based Soft Error tolerant Design for DNN accelerators
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Work-in-Progress Poster PaGO: Pareto-Assisted Goal Optimization for Analog Circuit Sizing
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript Intermittent Systems at Small Scale: Execution Model and Design Guidelines
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Research Manuscript DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosis
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Synthesis of CFET Cell Library Leveraging Backside Metal Routing
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Engineering Presentation Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
Research Manuscript Asymmetric Predictive Testing for Aging in SRAMs
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Work-in-Progress Poster HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Head of Product, CAE/EDA
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Research Manuscript From Test to SLM Advanced Solutions
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Work-in-Progress Poster HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Work-in-Progress Poster Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript ALLMod: Exploring \underline{A}rea-Efficiency of \underline{L}UT-based \underline{L}arge Number \underline{Mod}ular Reduction via Hybrid Workloads
Research Manuscript ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum Devices
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Quantization
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Late Breaking Results Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Exhibitor Forum A Configurable ECAD Library Solution for All Users
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Work-in-Progress Poster AI-enabled Efficient Extraction of Entire Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Work-in-Progress Poster Edge Continual Learning with Mixed-Signal Gaussian Mixture-based Bayesian Neural Networks
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Research Manuscript DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge
Research Manuscript Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Identifying System-on-Chip Security Assets with Structure-Based Analysis
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Work-in-Progress Poster SwiftMax: Reducing Training Time for Learnable Softmax Alternative in Customized Acceleration
Research Manuscript Graphs & Topology: The New Frontier in AI Modeling
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
China
Research Manuscript Maximizing Energy Efficiency in Spiking Neural Networks: A Dynamic Joint Pruning Framework
Work-in-Progress Poster Unary Positional System: Flexible Balance of Hardware Area and Performance
Work-in-Progress Poster PipeSpec: Breaking Stage Dependencies in Hierarchical LLM Decoding
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Analytical Warpage-aware Multi-die Floorplanning for Advanced Package Designs
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Research Manuscript Quantum Breakthroughs Creating Game-Changing Applications
Work-in-Progress Poster An Efficient Wear-Leveling-Aware Parallel Allocator for Multiple Persistent Memory File Systems
Engineering Poster A DFT parallel test technology
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Breaking & Securing the Future: Advances in System & Hardware Security
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum Devices
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Work-in-Progress Poster A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Engineering Poster HBM Timing Methodology with Liberty LVF
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Research Manuscript AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
M
Engineering Presentation AACT: Automated Analog Coverage Tool for Mixed Signal Verification
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Work-in-Progress Poster LLM-based Soft Error tolerant Design for DNN accelerators
Research Manuscript CXL-Interplay: Unraveling and Characterizing CXL Interference in Modern Computer Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Work-in-Progress Poster An Efficient Wear-Leveling-Aware Parallel Allocator for Multiple Persistent Memory File Systems
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Engineering Presentation Revolutionizing Digital ASIC Design through AI
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Research Manuscript RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Work-in-Progress Poster Directed on-the-fly Validation of Hierarchical Cache Coherence Protocols
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
Sales Executive
Hands-On Training Session Enhance Perforce/Synopsys VCS Workflows Using AWS and AWS FSx for NetApp ONTAP
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Research Manuscript Building Pillars of Quantum Circuits: Synthesis, Simulation & Compilation
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript Navigating 3D, Clock Trees, and Shared Learning
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Engineering Poster 3D-IC Heterogeneous System Implementation using Virtuoso Studio and Integrity System Planner
Engineering Poster Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Research Manuscript AI Meets Silicon: Transforming Hardware Design through AI-Driven Innovation
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Research Special Session Multi-Scale Thermal-Mechanical Modeling of Advanced Chips
Work-in-Progress Poster PipeSpec: Breaking Stage Dependencies in Hierarchical LLM Decoding
Research Manuscript Approximate SMT Counting Beyond Discrete Domains
Research Special Session Towards Secure Data Management using Multi-cryptographic Solutions
Work-in-Progress Poster Dead Gate Elimination
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Work-in-Progress Poster PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Work-in-Progress Poster GAIA: A Generative AI Approach for Enabling Aircraft Digital Twin Creation
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Engineering Poster CDC-RDC Inter-operable collateral Standardization
Engineering Poster PPA Friendly Custom Repeater Tree Insertion for High-Speed Designs
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Engineering Poster Automated generation of ISO 21434 Verification Work Products
Engineering Poster Automation of Shmoo Engine based Pre-Si BDI Testing
Engineering Presentation Deterministic On Chip Variation Modeling of Clock Mesh
Engineering Poster Early Clock Network Jitter Estimation
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Work-in-Progress Poster Design-Aware Multi-Armed Bandit Approach for Automated Design Verification
Work-in-Progress Poster Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Work-in-Progress Poster EqBaB: Efficient Equivalence Verification for Compressed DNNs with Bound Propagation
Research Panel Navigating the Tides of Funding for Chips and System Design
Research Manuscript New Frontiers in Microarchitectural and Physical Attacks and Defenses
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster LightCROSS: A Secure and Memory Optimized Post-Quantum Digital Signature CROSS
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
VP of Solutions Engineering for Helix IPLM
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Poster Automated AI-ML based flow for Validated Constraint Generation for CDC/RDC
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Work-in-Progress Poster CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
VP, Semiconductor Industry
Exhibitor Forum Engineering the Semiconductor Digital Thread
Engineering Presentation Taming Formal to define the Verification Quality
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
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Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Work-in-Progress Poster Extending RISC-V based GPGPU for fast execution of regular data-intensive kernels
Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Work-in-Progress Poster HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Poster Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Research Manuscript Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Late Breaking Results Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript LLM Uprising: Fast & Furious
Engineering Presentation ML based PPA Push using XAI
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Work-in-Progress Poster Design-Aware Multi-Armed Bandit Approach for Automated Design Verification
Research Manuscript Exploring the Unchartered: From Chiplets to Architecture and Validation
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Engineering Poster Enhanced LVS Techniques for Fast Convergence and Optimized Design Cycles
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Work-in-Progress Poster TEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric Prediction
Engineering Poster Audit Flow: A fast quality checker tool for early design convergence
Work-in-Progress Poster HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Engineering Presentation Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
Research Manuscript Transformers: Rise of the Optimized Large Language Models
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Work-in-Progress Poster MetaGuard: Transforming Run-Time Hardware Trojan Detection using Meta Reinforcement Learning
Group Vice-President of Technology
Engineering Special Session AI-Enabled EDA for Chip Design
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Tutorial Quantum Computing Design Automation
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Work-in-Progress Poster Solving Multidimensional Partial Differential Equations on Quantum Hardware
Engineering Poster Soft Error Simulation Tools, From 45nm to 3nm
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Engineering Poster Optimizing Power Integrity with Smart PDN Framework
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Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Work-in-Progress Poster Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Work-in-Progress Poster POG: Parameter Optimization using Graph Neural Networks on Reinforcement Learning
Work-in-Progress Poster Self-Motivated Agents for Analog Circuit Optimization via Intrinsic Reward
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Research Manuscript LLM/DL Driven Analog Circuit Design and Analysis
Engineering Special Session CDC-RDC Inter-operable Collateral Standardization
Research Manuscript Data Oblivious CPU: Micro-architectural Side-channel Leakage-Resilient Processor
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Engineering Poster A DFT parallel test technology
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Poster A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
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DAC Pavilion Panel Building Secure Chips Without Jeopardizing Design Budgets and Schedules
Engineering Poster timing-aware smart PG fill
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Engineering Special Session AI-Enabled EDA for Chip Design
Work-in-Progress Poster Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
IEEE TCVLSI Co-chair
Engineering Poster timing-aware smart PG fill
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
IEEE TCVLSI Chair
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Research Manuscript SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Research Manuscript Mitigating Routability Problems in Complementary-FET-based VLSI Designs
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Work-in-Progress Poster eMamba: Efficient Acceleration of Mamba Models for Edge Computing
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Work-in-Progress Poster FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
Work-in-Progress Poster CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
Engineering Presentation An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
Engineering Presentation Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Research Manuscript FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA
Late Breaking Results Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
Research Manuscript Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Work-in-Progress Poster Advanced Detection of Hardware Trojans in Post-Layout ICs: A GDSII-Focused Methodology
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Analyst Presentation Accelerator Package and System Design For The AI Era
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Work-in-Progress Poster Multiple Row Buffer DRAM
Engineering Special Session SLM Is the New DFT – Are You Ready?
Engineering Poster HSTAF: Hierarchical Static Timing Analysis Flow
Engineering Presentation Enhancing PDK Library Validation with Machine Learning. A Novel Approach to Layout Comparison
Engineering Poster Real-time Process Margin-based Layout Optimization
Research Manuscript The Answer Is In-memory!? ... In the Memory? ... Memory? Find Out Here!
Work-in-Progress Poster TEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric Prediction
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Work-in-Progress Poster CPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware Vulnerability
Engineering Poster A DFT parallel test technology
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Poster A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Research Manuscript Cost-Distance Steiner Trees for Timing-Constrained Global Routing
Engineering Poster A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Engineering Poster Using Big Data and ML techniques to triage timing violations
Work-in-Progress Poster Designing and Evaluating HBM-aware NTT Accelerator
Research Manuscript Look Both Ways: New Directions in High-Level Synthesis and Approximate Computing
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Exhibitor Forum Mastering Modern Data Management: Insights and Case Studies
Work-in-Progress Poster Energy-Efficient, Real-Time Robotic Path Planning through FPGA Acceleration
Work-in-Progress Poster Advanced Detection of Hardware Trojans in Post-Layout ICs: A GDSII-Focused Methodology
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Research Special Session SambaNova SN40L: Unleashing Agentic AI with Dataflow
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Engineering Poster Automation of Shmoo Engine based Pre-Si BDI Testing
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript Adventures in PCBs, Partitioning, and Legalization!
Work-in-Progress Poster Deep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applications
DAC Pavilion Panel Design, Develop, Dominate: The CHIPS Act's Role in Semiconductor Innovation
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Work-in-Progress Poster High-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable Hardware
Engineering Poster Real-time Process Margin-based Layout Optimization
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Engineering Poster Improving Digital Design performance and area using DSO.ai
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
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Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM Systems
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Work-in-Progress Poster ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Work-in-Progress Poster SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript All Quiet on the Processor Front: Next-Gen Processor Security and Enclave Innovations
Research Manuscript BPUFuzzer: Effective Fuzz Testing for Branching Transient Execution Vulnerabilities of RISC-V CPU
Work-in-Progress Poster CPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware Vulnerability
Work-in-Progress Poster HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
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Engineering Poster A new methodology to generate a multitude of SoC configurations quickly
Work-in-Progress Poster Beyond Verilog: Agents for Emerging HDLs
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Research Manuscript Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Research Manuscript New Frontiers in Microarchitectural and Physical Attacks and Defenses
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Work-in-Progress Poster AdaMAP: Adaptive Hardware Mapping for Model Compression using Low-Rank Decomposition
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Work-in-Progress Poster CD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator Impurities
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Research Manuscript AI Under Attack: Enhancing Privacy, Robustness, and Trust in ML Systems
Work-in-Progress Poster Non-Negative AdderNet (NNAN): Can We Make DNNs More Secure and Efficient Without Multiplication?
Work-in-Progress Poster Deep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applications
Engineering Poster Guided Physical Power Optimization of AI Silicon
Engineering Poster Recipe Explorer: Crafting the Missing PD Flow Layer
Engineering Poster Real-time Process Margin-based Layout Optimization
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Work-in-Progress Poster Rethinking the Distribution of Outliers in Large Language Models: An In-depth Study
Engineering Presentation Novel TRNG Verification with a High-Performance Simulation Methodology
Engineering Poster IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
Research Special Session Architecture and Design Approaches towards Large-scale AI Hardware Acceleration
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Presentation Custom IP Blocks – The Lego Blocks of Digital Design
Engineering Poster Single Corner Mixed Voltage Functional Noise Analysis
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Work-in-Progress Poster Efficient Runtime Management of Crossbars for Path-based In-Memory Computing
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Engineering Presentation Robust Verification for Complex Liberty IP
Research Manuscript ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning
Work-in-Progress Poster ROPE-MLA: Row-Access Optimized Processing Element Machine Learning Accelerator
Engineering Poster Pre-Validation Tool: Minimizing Errors, Maximizing Efficiency
Engineering Poster Hierarchical Early Latchup Checking Flow
Engineering Poster A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
Work-in-Progress Poster HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Engineering Presentation UPF Guided Design Editing for Early Low Power Verification Sign Off
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Work-in-Progress Poster Transistor Placement Routability Prediction for Standard Cell Design
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Engineering Presentation AI and Chiplet/Multi-die: Verification Scalability and AI driven Automation
Research Manuscript ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Work-in-Progress Poster LUT-MM: An Efficient Lookup Table-Based Approach for Modular Multiplication
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Work-in-Progress Poster Beyond Verilog: Agents for Emerging HDLs
Work-in-Progress Poster SynAlign: Annotating HDLs with Synthesis Results
Engineering Presentation Verification Innovation: Shaping the Future of Design Validation
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Engineering Poster Automated QA for Standard Cell Libraries used in RAIN RFID Chips
Work-in-Progress Poster TEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric Prediction
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Work-in-Progress Poster Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript Optimizing Recovery Logic in Speculative HLS
Late Breaking Results Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
Research Manuscript ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI
Research Manuscript Storage Meets Computing Power for Advancing AI and Data Processing Efficiency
Engineering Poster Efficient Translation of OpenAccess Design Data to the OASIS® Format
Work-in-Progress Poster CLEAR-HD: Computationally Light and Effective Unlearning for Hyperdimensional Computing
Research Manuscript CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Exhibitor Forum The Renaissance of EDA Startups
Research Manuscript Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
Work-in-Progress Poster Accelerating device level synthesis of binarized convolutional neural networks
Work-in-Progress Poster SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
Research Manuscript PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
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Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Poster Confidentiality Assurance: A Key Component of Hardware Security
Engineering Presentation Efficient Reset Metastability SignOff Methodology
Engineering Presentation Formal and Static Verification: Stop Bugs Before They Think They're Invited
Research Special Session Advancing Quantum Computing for Tomorrow
Engineering Presentation A Leap Forward in Formal Verification Using Generative AI
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Work-in-Progress Poster Multiple Row Buffer DRAM
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Poster AI/ML Driven Optimization for Efficient ATPG in Large Scale Designs
Engineering Presentation A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment
Engineering Poster Accelerating analog connectivity verification with Jasper: comparing formal methods to mixed simulation
Engineering Presentation Enhancing verification throughput in random tests regression with a novel machine learning engine
Work-in-Progress Poster Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Research Manuscript Multicore Environment State Representation for Agent-Directed Test Generation
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Engineering Poster SigmaAV: High Global and Local Noise Coverage Solution for Power Integrity Signoff
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Research Special Session EDA for Heterogeneous Integration
Work-in-Progress Poster Speeding Up Global Placement Method by Integrating a Precorrected FFT Solver
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Work-in-Progress Poster Extending RISC-V based GPGPU for fast execution of regular data-intensive kernels
Work-in-Progress Poster TrustChain AI: A Privacy-Preserving Decentralized Architecture for Large Language Model Aggregation
Engineering Presentation TrustChain: Enabling Consensus-Driven Multitasking AI
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Research Manuscript Breakthroughs in VLSI: Power-Efficient AI and Revolutionary Circuitry
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Engineering Presentation Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
Research Manuscript "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
Work-in-Progress Poster MetaGuard: Transforming Run-Time Hardware Trojan Detection using Meta Reinforcement Learning
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Research Manuscript ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Engineering Presentation Back-end and System Considerations for Chiplets
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Work-in-Progress Poster Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Engineering Presentation Guided Vectorless with Multi vector profiling for Memory PDN convergence
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Work-in-Progress Poster Dead Gate Elimination
Engineering Poster Generative AI for improving the productivity in Analog & Mixed Signal design flows
Engineering Poster Method & Apparatus to Migrate Design Repositories into Cloud
Engineering Poster Optimizing Network Storage for AI-Powered EDA Deployments
Work-in-Progress Poster CD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator Impurities
Research Manuscript Storage Meets Computing Power for Advancing AI and Data Processing Efficiency
Engineering Presentation A Novel approach for workload based GPU datapath power optimization
Research Special Session AAA: Advanced AI Accelerators
Engineering Presentation ML based PPA Push using XAI
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Engineering Poster A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
Engineering Poster Activity-Based Power Density Optimization
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning
Research Manuscript CognitiveArm: Enabling Real-Time EEG-Controlled Prosthetic Arm Using Embodied Machine Learning
Research Manuscript Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Work-in-Progress Poster Extending RISC-V based GPGPU for fast execution of regular data-intensive kernels
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Engineering Poster Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
Work-in-Progress Poster A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
Work-in-Progress Poster Heterogeneous Approximate Multiplications: A New Frontier for Practical DNNs
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
Research Manuscript Turbocharging Deep Learning Training: Efficiency Meets Innovation
Work-in-Progress Poster SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
Engineering Presentation AUTOLNKGEN: Automated Random Linker File Generation Framework for Heterogenous SoC Verification & Validation
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Engineering Poster Portfolio Re-characterization using AI
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Work-in-Progress Poster Rethinking the Distribution of Outliers in Large Language Models: An In-depth Study
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Engineering Poster Confidentiality Assurance: A Key Component of Hardware Security
Research Manuscript Approximate SMT Counting Beyond Discrete Domains
Work-in-Progress Poster An Advanced Wait-Free Protocol for Data Communication and Consistency in Multi-Core Real-Time Embedded Systems
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Research Manuscript Exploring the Formal Frontier for Verification and Validation
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Work-in-Progress Poster LLM-based Soft Error tolerant Design for DNN accelerators
Engineering Poster HBM Timing Methodology with Liberty LVF
Work-in-Progress Poster Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and Scheduling
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Work-in-Progress Poster CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Work-in-Progress Poster Designing and Evaluating HBM-aware NTT Accelerator
Work-in-Progress Poster Efficiently Exploiting Inference Parallelism in Two-Sided Sparse CNNs for a High-Speed, Low-Cost Accelerator
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Work-in-Progress Poster HeadTile: A Scalable and Efficient Accelerator for Large Language Model Inference with 3D Memory Integration
Work-in-Progress Poster LLM-based Soft Error tolerant Design for DNN accelerators
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Work-in-Progress Poster A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Work-in-Progress Poster Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Work-in-Progress Poster Designing and Evaluating HBM-aware NTT Accelerator
Work-in-Progress Poster Fast random walk through reduction of absorbing Markov chain
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Work-in-Progress Poster Design guidelines of succinct pulse generators for scalable superconducting qubit controllers
Research Manuscript Models and Hardware for Machine Learning and Beyond
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
Research Manuscript All-in-memory Stochastic Computing using ReRAM
Late Breaking Results Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
Engineering Poster Automated generation of ISO 21434 Verification Work Products
Engineering Poster Automation of Shmoo Engine based Pre-Si BDI Testing
DAC Pavilion Panel Generative AI in Design & Verification: Are We Hallucinating or Innovating?
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript AI Under Attack: Enhancing Privacy, Robustness, and Trust in ML Systems
Research Special Session Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations
Work-in-Progress Poster CD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator Impurities
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Engineering Poster Audit Flow: A fast quality checker tool for early design convergence
Engineering Poster ENZO: Comprehensive DFT Methodology for MCU class of devices
Work-in-Progress Poster Early Mismatch Detection in Analog Layout Using PLS Netlist
Engineering Poster Activity-Based Power Density Optimization
Work-in-Progress Poster Early Mismatch Detection in Analog Layout Using PLS Netlist
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Engineering Poster Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Work-in-Progress Poster Out of The Box Techniques for Data Path Verification
Engineering Poster Congestion Free, Power Domain Aware Signal Multiplexing
Engineering Presentation MCP Induced Glitches
Research Manuscript Measurement-based uncomputation of quantum circuits for modular arithmetic
Research Manuscript Optimizing windowed arithmetic for quantum attacks against RSA2048
Engineering Poster Single Corner Mixed Voltage Functional Noise Analysis
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Engineering Poster Validation journey of SOC High Speed Interfaces: From sim to real device
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Work-in-Progress Poster I-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPU
Senior Solution Architect
Hands-On Training Session Enhance Perforce/Synopsys VCS Workflows Using AWS and AWS FSx for NetApp ONTAP
Work-in-Progress Poster Computing-In-Memory Dataflow for Minimal Buffer Traffic
Research Manuscript Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Work-in-Progress Poster Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Smarter Compute, Faster Inference: Optimizing AI Systems on Edge
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Late Breaking Results Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
Research Manuscript Logic Restructuring with Preserved Logic Blocks
Engineering Presentation Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
Engineering Presentation Taming Formal to define the Verification Quality
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Engineering Special Session AI-Enabled EDA for Chip Design
Work-in-Progress Poster OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
Engineering Special Session Keeping the Guard Up with Security across the Board
Engineering Presentation Accelerated SoC Level Android Home Screen Bring-up, System Software Development and Validation at Pre-Silicon with Advanced Hybrid Emulation Methodology
Engineering Poster Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
Engineering Poster Comprehensive solution for Optimizing and Accelerating Gate level simulation for complex SOCs
Engineering Presentation Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
Work-in-Progress Poster Leveraging Artificial Neural Networks for Accurate and Efficient Glitch Propagation Modeling
Hands-On Training Session Enabling Seamless Hybrid Cloud Transitions for EDA & Systems Design with Cadence True Hybrid Cloud
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Engineering Presentation From Devices to Debug - Modeling Thoughtful Design Practices
Research Manuscript FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Research Manuscript Back to the Future: Where Speed Meets Efficiency
Engineering Poster Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
Research Manuscript Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Special Session Advanced Packaging: Promise and the Needs
Work-in-Progress Poster Automating RTL generation using Agentic LLMs
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Work-in-Progress Poster Designing and Evaluating HBM-aware NTT Accelerator
Research Manuscript POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Work-in-Progress Poster TiLeR: Hardware-In-The-Loop Mitigation of Software Timing Side-Channel Vulnerabilities
China
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
Work-in-Progress Poster SwiftMax: Reducing Training Time for Learnable Softmax Alternative in Customized Acceleration
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
Engineering Special Session LLM Innovations: Mirage or Milestone ?
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Research Manuscript BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Research Manuscript HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Research Manuscript KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Work-in-Progress Poster AI-enabled Efficient Extraction of Entire Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Work-in-Progress Poster PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Work-in-Progress Poster FAxC: Exploiting Feature Approximation for Privacy Preservation in Human Activity Recognition
Research Manuscript Squeezing Placement from FPGAs, Macros, Down to the Cell Level
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Research Special Session LLMs: A Driving Force in Next Generation Digital Design Automation
T
Engineering Poster HSTAF: Hierarchical Static Timing Analysis Flow
Research Manuscript To Abstract or Not to Abstract the Storage Layer
Work-in-Progress Poster Heterogeneous Approximate Multiplications: A New Frontier for Practical DNNs
Work-in-Progress Poster Towards Accurate, Real-Time, and Energy-Efficient Attention Monitoring
Research Special Session On the Limitations of VLSI Structural Manufacturing Test and Future Directions
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Work-in-Progress Poster Analytical Optimization for Robust and Efficient Analog IC Design Automation
Work-in-Progress Poster Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Tutorial Quantum Computing Design Automation
Research Manuscript Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript Innovative Techniques for Analog Circuit Simulation and Optimization
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Work-in-Progress Poster Scalar Runahead
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Engineering Presentation Novel Clocks and Resets Architecture Model
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Chair, ECE Department; Co-Founder
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Work-in-Progress Poster Enabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AI
Engineering Presentation AI-aided flow for digital verification of a multiprotocol SerDes PHY
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Research Manuscript Follow the Logic: Advances in Logic Synthesis
Engineering Special Session AI-Enabled EDA for Chip Design
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Research Manuscript Pushing Quantum Computing Reality from Routing to Error Corrections and QML
Work-in-Progress Poster Quantum Properties Trojans (QuPTs) for Attacking QNNs
Research Special Session Materials-Device-Systems Co-optimization using AI/ML
Work-in-Progress Poster Efficient Runtime Management of Crossbars for Path-based In-Memory Computing
Research Special Session Enhancing Design Automation with AI and Quantum Algorithms for Chip Design
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Engineering Presentation Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Work-in-Progress Poster Automating RTL generation using Agentic LLMs
Senior Director
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Research Manuscript Ready, Set, Scale! AI's Journey from Edge to Cloud Optimization
Research Manuscript SuperCopyback: Revisiting Copyback on Modern NAND Flash-based SSDs
Work-in-Progress Poster Deep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applications
Engineering Poster Real-time Process Margin-based Layout Optimization
Engineering Special Session The Evolution of Collaborative Open Source Hardware Development
Research Manuscript Clearance-Constrained PCB Global Placement with Heterogeneous Components
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Research Manuscript FT-MUX: A Fault-Tolerant Microfluidic Multiplexer
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Research Manuscript Right on Time, Built to Last: New Frontiers in Critical System Design
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
U
Research Manuscript A Novel Covert Timing Channel for Cloud FPGAs
Engineering Poster 18% Die area reduction in UWB Automotive Production SoC meeting performance
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Engineering Presentation Securing Chiplet Integration: A System-in-Package Security Architecture.
Research Manuscript VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Research Manuscript WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Engineering Poster Silicon Lifecycle Management in Automotive Design
Engineering Poster Audit Flow: A fast quality checker tool for early design convergence
Engineering Presentation Grid Resilience - Powering Solutions Design and Delivery for the Performance Promises
Engineering Poster Single Corner Mixed Voltage Functional Noise Analysis
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
V
Work-in-Progress Poster Leveraging Artificial Neural Networks for Accurate and Efficient Glitch Propagation Modeling
Engineering Poster Solving Configuration Challenge with SVRAND Verification Flow
Engineering Presentation Logic and SRAM Library Generation and Analysis for Digital Design Enablement
Engineering Poster Portfolio Re-characterization using AI
Engineering Presentation Robust Verification for Complex Liberty IP
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Research Manuscript DCO-3D: Differentiable Congestion Optimization in 3D ICs
Exhibitor Forum The Generative AI Revolution in Semiconductor Development
Work-in-Progress Poster Boolean Reasoning Guided Ungrouping
Engineering Presentation IP Gold – New Digital Design Nuggets
Research Manuscript LA-MTL: Latency-Aware Automated Multi-Task Learning
Research Manuscript SuperFast: Fast Supernet Training using Initial Knowledge
Engineering Poster An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
Research Manuscript DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Work-in-Progress Poster GraCo - A Graph Composer for Integrated Circuits
Work-in-Progress Poster Schemato - An LLM for Netlist-to-Schematic Conversion
Work-in-Progress Poster CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
Work-in-Progress Poster DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
Work-in-Progress Poster Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
Research Manuscript GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
Engineering Poster Confidentiality Assurance: A Key Component of Hardware Security
Analyst Presentation View from Wall Street
Engineering Presentation Enhanced Power Saving with System-on-Chip and Software Design Optimization
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
W
Engineering Presentation A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
Engineering Poster Agentic AI Approach to Optimize Front-End EDA Tools Flow
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Work-in-Progress Poster HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
China
Research Manuscript A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Late Breaking Results Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Manuscript Models and Hardware for Machine Learning and Beyond
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript Real-Time Dynamic IR-drop Prediction for IR ECO
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Work-in-Progress Poster LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
Tutorial Quantum Computing Design Automation
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster Scalar Runahead
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Engineering Poster A X-mask Chip Fast Binning Technology
Work-in-Progress Poster EvoSolo: Evolutionary Sequence Optimization for Logic Synthesis with Cascaded PPO
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Engineering Presentation Efficient Hardware Fuzzing based on SystemC
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Special Session LLMs Meet Post-Silicon Test Engineering: A New Era
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Work-in-Progress Poster IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
China
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
Research Manuscript HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Research Manuscript ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Engineering Presentation Novel Clocks and Resets Architecture Model
Engineering Poster A DFT parallel test technology
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Engineering Presentation Efficient Automation Strategy for Package Substrate Routing
Research Manuscript GPart: A GNN-Enabled Multilevel Graph Partitioner
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Research Manuscript Construction of DAG Models for Autonomous Systems
Engineering Special Session AI-Enabled EDA for Chip Design
Founder & CEO
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Work-in-Progress Poster Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning Framework
Research Manuscript On Bit-level Reverse Engineering of Vehicular CAN Bus
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Work-in-Progress Poster Scalar Runahead
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Research Manuscript Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
Research Manuscript Leveraging the Memory Hierarchy for Emerging Applications and Hardware
Research Manuscript MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Research Manuscript Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models
Work-in-Progress Poster One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
Research Manuscript The Unwritten Contract of Cloud-based Elastic Solid-State Drives
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
Research Manuscript DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosis
Research Manuscript Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
Research Manuscript Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
Research Manuscript Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
Research Manuscript SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Work-in-Progress Poster Crosstalk-Aware Mapping for Optical Neural Networks
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript ALLMod: Exploring \underline{A}rea-Efficiency of \underline{L}UT-based \underline{L}arge Number \underline{Mod}ular Reduction via Hybrid Workloads
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Quantization
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Tutorial Quantum Computing Design Automation
Research Panel Navigating the Tides of Funding for Chips and System Design
Engineering Presentation PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
Research Manuscript FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster Scalar Runahead
Work-in-Progress Poster Guard Ring- and Diffusion-Sharing Embedded FinFET Array Placement
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Ancillary Meeting OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Work-in-Progress Poster Panther: A PIM-based Blockchain Database System Supporting Efficient Verifiable Queries
Work-in-Progress Poster Unary Positional System: Flexible Balance of Hardware Area and Performance
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Chief Product Officer
Engineering Presentation IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Research Manuscript Leveraging the Memory Hierarchy for Emerging Applications and Hardware
Research Manuscript P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Research Manuscript Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Engineering Poster Automated IR convergence with PrimeClosure IR-ECO
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript Scaling, Learning, and Parallelizing the Future of Verification and Synthesis
Research Manuscript Cross-Attention for AES Mode Variation in Side-Channel Analysis
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Work-in-Progress Poster ROPE-MLA: Row-Access Optimized Processing Element Machine Learning Accelerator
Work-in-Progress Poster An Efficient Wear-Leveling-Aware Parallel Allocator for Multiple Persistent Memory File Systems
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Special Session Energy-Efficient On-Device AI Acceleration and More Enabled By 3D Integration
Research Manuscript Generative Model Based Standard Cell Timing Library Characterization
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Engineering Presentation Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
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Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Engineering Poster A DFT parallel test technology
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Work-in-Progress Poster ScaleX: A Scalable and Flexible Architecture for Efficient GNN Inference
Work-in-Progress Poster EqBaB: Efficient Equivalence Verification for Compressed DNNs with Bound Propagation
Engineering Presentation Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Research Manuscript CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Power-Based Side-Channel Attack on XGBoost Accelerator
China
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
China
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Research Manuscript AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Research Manuscript Breakthroughs in Timing Prediction, Analysis, and Optimization
Work-in-Progress Poster DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript Ensembler: Protect Collaborative Inference Privacy from Model Inversion Attack via Selective Ensemble
Work-in-Progress Poster PI-Whisper: Designing an Adaptive and Incremental Automatic Speech Recognition System for Edge Devices
Research Manuscript Ready, Set, Scale! AI's Journey from Edge to Cloud Optimization
Work-in-Progress Poster AI-enabled Efficient Extraction of Entire Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Exhibitor Forum Intelligent Extraction of Advanced IC Package
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Work-in-Progress Poster MERINDA: Model Recovery in FPGA based Dynamic Architecture
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors*
Work-in-Progress Poster Designing and Evaluating HBM-aware NTT Accelerator
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
Research Manuscript A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Work-in-Progress Poster HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Work-in-Progress Poster Crosstalk-Aware Mapping for Optical Neural Networks
China
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Research Manuscript Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Work-in-Progress Poster Scalar Runahead
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Research Manuscript Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Research Manuscript Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Research Manuscript A PulseWidth-IN-PulseWidth-Out Universal Nonlinear Processing Element for Time-Domain In-Memory Computing Systems
Research Manuscript RAGNAR: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Work-in-Progress Poster ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
Work-in-Progress Poster HeadTile: A Scalable and Efficient Accelerator for Large Language Model Inference with 3D Memory Integration
Work-in-Progress Poster LLM-based Soft Error tolerant Design for DNN accelerators
Y
Engineering Poster IR-Aware Timing Analysis using Accurate DvD-PWL Flow for Advanced Technology Nodes
Engineering Poster Silicon Lifecycle Management in Automotive Design
Engineering Poster timing-aware smart PG fill
Engineering Presentation Reconfigurable Vector Floating Point Accelerator on FPGAs
Work-in-Progress Poster MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
Engineering Presentation Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
Work-in-Progress Poster OpenGC: An Open-Source Gain Cell Compiler
Work-in-Progress Poster Investigating Security Breaches in Vehicle Infotainment Systems
Research Manuscript A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
Engineering Presentation 3DIC Thermal-Aware Early Design Optimization
Research Manuscript BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster MTrace : Trusted logging using ARM DWT on embedded devices
Research Manuscript AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
Research Manuscript Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis
Research Manuscript GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Research Manuscript Turbocharging Deep Learning Training: Efficiency Meets Innovation
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Research Manuscript Program, Debug, Accelerate: Software Innovations
Work-in-Progress Poster Blaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum Circuits
Research Manuscript DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Research Manuscript DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Research Manuscript Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
Work-in-Progress Poster LPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT Algorithm
Work-in-Progress Poster NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
Work-in-Progress Poster LUT-MM: An Efficient Lookup Table-Based Approach for Modular Multiplication
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Research Manuscript The Unwritten Contract of Cloud-based Elastic Solid-State Drives
Research Manuscript BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
Research Manuscript PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
Research Manuscript Property-driven Parallel Symbolic Model Checking of LTL
Research Manuscript Hybrid Embedding Framework for Memory-Efficient Recommendation Systems
Engineering Presentation Generative-AI Technology for block and SoC IR closure: Root-Cause and Repair strategies
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Work-in-Progress Poster Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Late Breaking Results Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
Research Manuscript Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
Engineering Special Session Neuromorphic Testbeds: Pioneering Energy-Efficient Computing for the Future
Research Manuscript Smarter Compute, Faster Inference: Optimizing AI Systems on Edge
Work-in-Progress Poster EqBaB: Efficient Equivalence Verification for Compressed DNNs with Bound Propagation
China
Research Manuscript Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
Research Manuscript Hypnos: Memory Efficient Homomorphic Processing Unit
Research Manuscript GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Research Manuscript Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
Work-in-Progress Poster PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
China
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Research Manuscript 3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs
Research Manuscript 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Research Manuscript Neural Scaling Laws for Graph Neural Networks in Atomistic Materials Modeling
Engineering Special Session Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
Research Manuscript PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Research Manuscript Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Research Manuscript Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Manuscript FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Engineering Presentation Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
Research Manuscript PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
Research Manuscript GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Work-in-Progress Poster MPE : A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression Scheme
Work-in-Progress Poster PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Research Manuscript PatLabor: Pareto Optimization of Timing-Driven Routing Trees
Research Manuscript Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems
Research Manuscript FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization
Research Manuscript FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUT
Research Manuscript Shaping Tomorrow: Co-Designing Emerging Technologies for Computing and Beyond
Research Manuscript Everything About LLM and Transformer Accelerators
Engineering Presentation A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits
Work-in-Progress Poster An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Late Breaking Results Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Research Manuscript Mitigating Routability Problems in Complementary-FET-based VLSI Designs
Engineering Presentation Enhancing Verification Efficiency with Garbage-Model Methodology
Research Manuscript MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster Scalar Runahead
China
Research Manuscript Maximizing Energy Efficiency in Spiking Neural Networks: A Dynamic Joint Pruning Framework
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Work-in-Progress Poster Unary Positional System: Flexible Balance of Hardware Area and Performance
Engineering Presentation Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
Work-in-Progress Poster Approximation-based Inter-PE Communication-free Image Filtering for Commodity PIM
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript MOSS: Multi-Modal Representation Learning on Sequential Circuits
Research Manuscript Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation*
Research Manuscript E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Research Manuscript ML-Powered Logic Synthesis
Engineering Presentation Fear Not! With LLMs, Learning PSS Isn't Scary At All
Research Manuscript Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
Work-in-Progress Poster A Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Work-in-Progress Poster A Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic Accelerator
Research Manuscript A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Research Manuscript LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
Research Manuscript Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Research Manuscript Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models
Work-in-Progress Poster ScaleX: A Scalable and Flexible Architecture for Efficient GNN Inference
Work-in-Progress Poster FAxC: Exploiting Feature Approximation for Privacy Preservation in Human Activity Recognition
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Work-in-Progress Poster MemSearch: An Efficient Memristive In-memory Search Engine with Configurable Similarity Measures
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Research Manuscript A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript Balancing Speed and Memory: Advancing LLM Acceleration
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Work-in-Progress Poster Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Work-in-Progress Poster FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Work-in-Progress Poster PPA-driven Placement via Adaptive Cluster Constraints Optimization
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Research Manuscript ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating
Research Manuscript smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Work-in-Progress Poster dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUs
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
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Work-in-Progress Poster Beyond Verilog: Agents for Emerging HDLs
Exhibitor Forum The Renaissance of EDA Startups
Work-in-Progress Poster LLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-Gen
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Engineering Poster A DFT parallel test technology
Research Manuscript Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration
Research Manuscript MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing
Research Manuscript New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Work-in-Progress Poster HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
Work-in-Progress Poster ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Research Manuscript Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript iG-kway: Incremental k-way Graph Partitioning on GPU
Engineering Poster A DFT parallel test technology
Research Manuscript APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Research Manuscript Breaking & Securing the Future: Advances in System & Hardware Security
Work-in-Progress Poster IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
Work-in-Progress Poster Speeding Up Global Placement Method by Integrating a Precorrected FFT Solver
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
Research Manuscript An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Research Manuscript IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
Engineering Presentation Machine Learning based Dynamic IR hotspot estimation for SoC Designs
Engineering Poster Physical Design Independent-IR solver for early first cut SoC PG analysis
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
Research Manuscript Multi-Agent Yield Analysis For Circuit Design
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript DroidFuzz: Proprietary Driver Fuzzing for Embedded Android Devices
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Work-in-Progress Poster Navigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low Energy
Work-in-Progress Poster PipeSpec: Breaking Stage Dependencies in Hierarchical LLM Decoding
Work-in-Progress Poster Rethinking the Distribution of Outliers in Large Language Models: An In-depth Study
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Work-in-Progress Poster CPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware Vulnerability
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Work-in-Progress Poster SwiftMax: Reducing Training Time for Learnable Softmax Alternative in Customized Acceleration
Work-in-Progress Poster LPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT Algorithm
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Research Manuscript CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Work-in-Progress Poster CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
Work-in-Progress Poster LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
Research Manuscript AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
Research Manuscript LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Research Manuscript ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript X-SAT: An Efficient Circuit-Based SAT Solver
Research Manuscript A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
Work-in-Progress Poster TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
China
Work-in-Progress Poster Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript On Design Space Exploration of Cache System in Multi-Chiplet Systems
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Research Manuscript SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Research Manuscript Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Work-in-Progress Poster Rethinking Translation Robustness for Reliable Convolutional Segmentation Architecture
Research Manuscript CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
Work-in-Progress Poster Combining Physics-Informed and Data-Driven Learning for Efficient Modeling of Memristive Devices
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript SIMAX: Accelerating RTL Simulation for Large-Scale Design
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript Power-Constrained Printed Neuromorphic Hardware Training
Work-in-Progress Poster GRL: Redesign Distributed Reinforcement Learning Training on One GPU
Research Manuscript ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Research Manuscript AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
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Work-in-Progress Poster Ordering-Centric: A Scalable and Exact Method for Scheduling with Resource Constraints
Research Manuscript CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error Correction
Research Manuscript ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
Research Manuscript MemSeer: Leveraging Memory Failure Distinctions and Multi-Grained Prediction in Ultra-Scale Heterogeneous X86/ARM Clusters
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Work-in-Progress Poster HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
Research Manuscript HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Research Manuscript IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
Work-in-Progress Poster ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
Research Manuscript VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Work-in-Progress Poster Scalar Runahead
Research Manuscript MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Work-in-Progress Poster IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
Research Manuscript Breakthroughs in Timing Prediction, Analysis, and Optimization
Engineering Poster Method of Constraint Transformation in Static Timing Analysis for Dual Edge Timing
Engineering Poster Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Work-in-Progress Poster HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
Research Manuscript Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
Work-in-Progress Poster Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Research Manuscript MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Research Manuscript 3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Research Manuscript A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
Research Manuscript LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Research Manuscript PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Work-in-Progress Poster PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Research Manuscript Curvilinear Optical Proximity Correction via Cardinal Spline
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Late Breaking Results Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Research Manuscript NVR: Vector Runahead on NPUs for Sparse Memory Access
Work-in-Progress Poster PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript Hardware-Software Co-design for Distributed Quantum Computing
Research Manuscript ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
Engineering Poster A DFT parallel test technology
Engineering Poster A Solution for intermittently and Fastly Power On Repair
Engineering Poster A X-mask Chip Fast Binning Technology
Engineering Presentation A novel structure to achieve broadcastable IJTAG network
Engineering Poster Active Device Testkeys Enable FEOL-Process Monitoring and Performance Improvement
Research Manuscript RE3: Finding Refinement Relations with Relational Mapping Abstraction
Research Manuscript Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Research Manuscript Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Research Manuscript UVLLM: An Automated Universal RTL Verification Framework using LLMs
Research Manuscript CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Research Manuscript SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Research Manuscript DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Work-in-Progress Poster Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Research Manuscript LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
Research Manuscript GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
Engineering Presentation Routing Congestion Mitigation Techniques Targeting Dense Designs
Research Manuscript Faster, Safer, Greener: AI-driven Evolution in Smart Edge
Research Manuscript ML-Powered Logic Synthesis
Research Manuscript Scalable Community Detection Using QHD and QUBO Formulation
Research Manuscript XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
Research Manuscript Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Research Manuscript AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
Work-in-Progress Poster Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
Research Manuscript An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Late Breaking Results Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Research Manuscript UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Work-in-Progress Poster Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
Work-in-Progress Poster A PCA and KDE Based Approach for Statistical CMOS Compact Model Parameter Generation
Work-in-Progress Poster An Advanced Wait-Free Protocol for Data Communication and Consistency in Multi-Core Real-Time Embedded Systems
Work-in-Progress Poster Automotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)
Work-in-Progress Poster An Efficient Wear-Leveling-Aware Parallel Allocator for Multiple Persistent Memory File Systems
Research Manuscript Speculative Decoding for Verilog: Speed and Quality, All in One
Research Manuscript LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
Research Manuscript SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Research Manuscript Efficient Continuous Logic Optimization with Diffusion Model
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Research Manuscript Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Work-in-Progress Poster AI-enabled Efficient Extraction of Entire Advanced IC Package
Engineering Presentation High Performance Extraction of 2.5D/3D-IC Package
Research Manuscript Leveraging Critical Proof Obligations for Efficient IC3 Verification
Engineering Presentation SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
Work-in-Progress Poster GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Research Manuscript SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
Work-in-Progress Poster GTA: An Instruction-Driven Graph Tensor Accelerator for General GNNs
Research Manuscript A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition
Research Manuscript Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems
Research Manuscript FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization
Research Manuscript FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUT
Research Manuscript From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Research Manuscript H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
Engineering Special Session Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
Work-in-Progress Poster EMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity Awareness
Research Manuscript DSPlacer: DSP Placement for FPGA-based CNN accelerator
Research Manuscript Routability-aware Packing for High-density Nonvolatile FPGAs
Research Manuscript Circuit Breakers: Secrets Unleashed!
Late Breaking Results Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Work-in-Progress Poster Genesis: A Spiking Neuromorphic Accelerator With On-chip Continual Learning