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Organization

NXP Semiconductors
Contributors
Ertugrul Demircan
Shining Dong
Abhinav Gaur
Pramod Gayakwad
Glen Ge
Ravi J N
Dinesh Joshi
Santhosh Kamatam
Reshma Krishnakumar
Swanand Kulkarni
Akhilesh Mishra
Vandana Narula
Khushboo Rathore
Abhishek Sharma
Nidhi Sinha
Presentations
Engineering Poster
An Efficient Hierarchical Chip-Top Level EMIR Signoff Methodology for Large Automotive SOCs.
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
An Efficient Methodology of Analyzing Rush Current in Power Gated Design
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Congestion Free, Power Domain Aware Signal Multiplexing
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Enhanced LVS Techniques for Fast Convergence and Optimized Design Cycles
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Enhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros/IP and Standard Cell Libraries
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Innovative and Cost-Effective Approach to ESD Reliability Verification in the Cloud
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
MCP Induced Glitches
11:45am - 12:00pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Presentation
Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
4:00pm - 4:15pm PDT Monday, June 23 2010, Level 2
IP
Engineering Poster
Portfolio Re-characterization using AI
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Power-aware DFT-driven High Confidence EMIR Signoff for Low Power Automotive SoCs
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Robust Verification for Complex Liberty IP
4:45pm - 5:00pm PDT Monday, June 23 2010, Level 2
IP