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Organization

Google
Contributors
Hao Chen
Frédéric Didier
Sandeep Gajbhare
Sainath Reddy Gummana
akshay gupta
Mohammed Hafiz
Megha Hansaliya
Mathew Kaipanatu
Smaritha Kasukurthi
Rakesh Kinger
Sravanth Mucharla
Sathya Narasimhan
Prateek Pendyala
Laurent Perron
T Govindaswamy Rahul Sai
Shruti Rakheja
Alina Sebastian
Cheng Tan
Xiaoqing Xu
Jingwei Zhang
Xiaofan Zhang
Presentations
Engineering Poster
Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Accurate Memory IR Sign-Off at Lower Tech nodes
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
EDA in the Cloud: Optimizing Chip Design Workflows with Google Cloud Platform
11:15am - 11:45am PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Presentation
Guided Vectorless with Multi vector profiling for Memory PDN convergence
1:45pm - 2:00pm PDT Monday, June 23 2012, Level 2
AI
Back-End Design
Chiplet
Engineering Presentation
Identifying Soft-Resets in Design using RDC Tool Flow
2:00pm - 2:15pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Engineering Presentation
Logic and SRAM Library Generation and Analysis for Digital Design Enablement
3:45pm - 4:00pm PDT Monday, June 23 2010, Level 2
IP
Engineering Presentation
Machine Learning based Dynamic IR hotspot estimation for SoC Designs
2:00pm - 2:15pm PDT Monday, June 23 2012, Level 2
AI
Back-End Design
Chiplet
Engineering Poster
Maximizing IR sign-off coverage using Sigma-AV and its benefit on PPA
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Special Session
Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
10:30am - 12:00pm PDT Monday, June 23 2012, Level 2
Front-End Design
Chiplet
Engineering Poster
Physical Design Independent-IR solver for early first cut SoC PG analysis
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
5:00pm - 5:15pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model Training
2:00pm - 2:15pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Research Manuscript
TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology
2:45pm - 3:00pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification