Close

Organization

Intel Corporation
Contributors
Anila Azam
Suvadeep Banerjee
Sardar Bhukya
Naveen Bishnoi
Sneha Biswas
Yi Wei Chen
Yi-Wei Chen
Debendra Das Sharma
Keshavkumar Durgakeri
Anil kumar Ede
Anilkumar Ede
Jason Fung
Sravanthi Gajjala
Mark Gallina
Rangarajan Govindan
Sarala Gumma
Ming-Chuan Hu
Wei-Yi Hu
Wei-Yi Willy Hu
Chien-Chih Huang
Dean Huang
Po-Hsiang Huang
Lalitha Immaneni
Lalitha Immaneni
Prakeerthi Jallipalli
Bhargav Korrapati
R Santhosh Kumar
Rakesh Kumar
Shamik Kundu
Souvik Kundu
Kuan-Ting Kuo
Athmanarayanan Lakshmi Narayanan
Avner Landver
Rui Li
Yi-Shan Li
Chee How Lim
Chia-Yi Liou
Deepak Mathaikutty
Pietro Mercati
sachin mirajkar
Suriya Natarajan
Iredamola Olopade
Sivaraman P
Lakshmi Sarvaani Pallapu
Mondira Pant
Saidesh Pasupuleti
Chung-Ching Peng
Arnab Raha
Vivek Rajan
Venkatesh Ramamurthy
Mohit Rawat
A S Ramkumar Reddy
A Subbaramkumar Reddy
Gaurav Reddy
Paritosh Saxena
Julien Sebot
Manoj Selva
Satish Sethuraman
Karanvir Singh
Nilabh Srivastava
Mahesh Subedar
Dipto Thakurta
Omesh Tickoo
Roopa Tigadi
Yu-Wei Tseng
Andy Wei
Chih-Hsiang Yang
Jianfang Zhu
Xia Zhu
Session Chairs
Chandrakanth Betageri
Navid Farazmand
Amol Joshi
Qian Wang
Presentations
Research Manuscript
"OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
2:00pm - 2:15pm PDT Monday, June 23 3006, Level 3
Security
SEC3: Hardware Security: Attack & Defense
Engineering Poster
Networking
"Optimizing Timing Convergence in High-Speed PCIe Systems: An EDA Methodological Approach"
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
3D-IC Stacking and Floorplan Design Methodology through ML-based Pre-trained Model and Practical Macro Placement Framework for Performance and Thermal Co-optimization
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Presentation
3DIC Thermal-Aware Early Design Optimization
4:00pm - 4:15pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Special Session
A Look into the Future of Verification
1:30pm - 3:00pm PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Poster
Networking
A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
A Novel Power-gradient-aware Cell Placement Methodology Considering 3D-IC Stacking Thermal Boundary to Achieve Timing and Thermal Co-optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Poster
Networking
Activity-Based Power Density Optimization
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Special Session
Advanced Package Design & System Co-Optimization for Heterogeneous Integration
3:30pm - 4:00pm PDT Tuesday, June 24 3010, Level 3
Design
DAC Pavilion Panel
AI and VLSI: A Symbiotic Revolution Enriching Our Lives and Shaping Our Future
3:00pm - 3:45pm PDT Tuesday, June 24 DAC Pavilion, Level 2 Exhibit Hall
Engineering Presentation
Analysis of Electrostatic Discharge (ESD) for 3DIC systems
4:15pm - 4:30pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Networking
Work-in-Progress Poster
Automating RTL generation using Agentic LLMs
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Special Session
CDC-RDC Inter-operable Collateral Standardization
10:30am - 12:00pm PDT Monday, June 23 2008, Level 2
Back-End Design
Engineering Poster
Networking
Design Floorplan-Driven Localization of SMS Processors for Optimized Memory Performance
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
Dyna-Optics: Architecting a Channel-Adaptive DNN Near-Sensor Optical Accelerator for Dynamic Inference
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Presentation
Efficient Reset Metastability SignOff Methodology
2:30pm - 2:45pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Engineering Special Session
Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
1:30pm - 3:00pm PDT Monday, June 23 2008, Level 2
AI
Back-End Design
Chiplet
Engineering Poster
Networking
Enhancing Timing Closure in High-Frequency Designs through Precise Latency Control and Timing-Aware Sink Assignment
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Formal Property Verification on Xeon SoC owned IPs
1:45pm - 2:00pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Engineering Presentation
Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
3:45pm - 4:00pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Engineering Poster
Networking
Machine Learning accelerated distributed computing Place and Route framework for High Performance CPU designs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
1:45pm - 2:00pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Engineering Special Session
Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
10:30am - 12:00pm PDT Monday, June 23 2012, Level 2
Front-End Design
Chiplet
Networking
Work-in-Progress Poster
OpenAssert: Towards Open-Source Large Language Models for Assertion Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
2:00pm - 2:15pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
PipeLink: a pipelined resource sharing system for dataflow high-level synthesis
1:30pm - 1:45pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Engineering Presentation
PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage
4:30pm - 4:45pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Poster
Networking
PPA Friendly Custom Repeater Tree Insertion for High-Speed Designs
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Research Panel
Security for/with Hardware – (Why) Haven't We Already Solved This?
1:30pm - 3:00pm PDT Tuesday, June 24 3012, Level 3
Security
Ancillary Meeting
Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
4:00pm - 5:00pm PDT Tuesday, June 24 2004, Level 2
Engineering Presentation
SuperCoverage: AI-Guided Full Coverage of Thermal and Power Analysis for SoC Design
4:00pm - 4:15pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Sessions
Engineering Presentation
Surviving Monte Carlo – Circuit Optimization Ideas
10:30am - 12:00pm PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Presentation
Watt's Next: Low-Power Design and Verification Trends
10:30am - 12:00pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Engineering Presentation
From Devices to Debug - Modeling Thoughtful Design Practices
10:30am - 12:00pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Research Manuscript
Of Circuits and Secrets: Emerging Hardware Security Primitives and Cryptographic Accelerators
1:30pm - 3:00pm PDT Wednesday, June 25 3008, Level 3
Security
SEC2: Hardware Security: Primitives & Architecture, Design & Test