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Organization

Hong Kong University of Science and Technology (HKUST)
Contributors
Afzal Ahmad
Huangxu Chen
Tim Cheng
Haochen Du
Wenji Fang
Jinming Ge
Mengming Li
Wenkai Li
Jiawei Liang
Shang Liu
Yao Lu
Dimitrios Tsaras
Jing WANG
Yuan Xie
Zhiyao Xie
Jiangnan Yu
Qijun Zhang
Wei Zhang
Wei Zhang
Presentations
Research Manuscript
An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models
5:15pm - 5:30pm PDT Tuesday, June 24 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
4:45pm - 5:00pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Research Manuscript
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
2:00pm - 2:15pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
5:15pm - 5:30pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Networking
Work-in-Progress Poster
CPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware Vulnerability
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
4:30pm - 4:45pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
HIVE: A Hierarchical Inverse Graph Construction Framework for Verilog Code Generation and Compilation Error Correction Using Large Language Models
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Tutorial
Introduction to Foundation AI Model and Its EDA Applications
1:30pm - 5:00pm PDT Sunday, June 22 3004, Level 3
Sunday Program
Research Manuscript
McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMs
4:15pm - 4:30pm PDT Monday, June 23 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Networking
Work-in-Progress Poster
MPE : A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression Scheme
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Panel
Navigating the Tides of Funding for Chips and System Design
10:30am - 12:00pm PDT Monday, June 23 3012, Level 3
Design
Research Manuscript
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
2:00pm - 2:15pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Phoenix: Pauli-based High-level Optimization Engine for Instruction Execution on NISQ devices
2:15pm - 2:30pm PDT Monday, June 23 3003, Level 3
Design
DES6: Quantum Computing
Research Manuscript
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
2:30pm - 2:45pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure