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Organization

City University of Hong Kong
Contributors
Arindam Basu
Shuai Dong
Zhengnan Fu
Nan Guan
Yu Mao
Guan Nan
Juxin Niu
Hongyang Shang
Dongdong Tang
Jun Wang
Ning Wang
Weilan Wang
Junyi Yang
Bingkun Yao
Presentations
Research Manuscript
Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
4:45pm - 5:00pm PDT Monday, June 23 3008, Level 3
Systems
SYS2: Design of Cyber-Physical Systems and IoT
Research Manuscript
DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based Filtering
3:30pm - 3:45pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Research Manuscript
Easz: An Agile Transformer-based Image Compression Framework for Resource-constrained IoTs
3:45pm - 4:00pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Research Manuscript
High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References
10:30am - 10:45am PDT Tuesday, June 24 3003, Level 3
Design
DES2A: In-memory and Near-memory Computing Circuits
Research Manuscript
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
4:15pm - 4:30pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
5:15pm - 5:30pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS3: Embedded Software
Research Manuscript
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
11:00am - 11:15am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
UVLLM: An Automated Universal RTL Verification Framework using LLMs
4:30pm - 4:45pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies