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Organization

Western Digital
Contributors
Sarah Ahmad
Himanshu Bansal
Jason Chow
Ayan Datta
pradeep kothari
Tusharkant Mishra
Manjunath Nayak
Pardhu Pavan
Anoop Singh
Vikash T
Subhash Uppala
Presentations
Engineering Poster
Audit Flow: A fast quality checker tool for early design convergence
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Autonomous Physical Design: Accelerating ASIC Design using Machine Learning
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Deterministic On Chip Variation Modeling of Clock Mesh
2:30pm - 2:45pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Poster
Networking
Early Clock Network Jitter Estimation
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
HSTAF: Hierarchical Static Timing Analysis Flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
STA Dashboard: Leveraging Data Analytics for Effective Static Timing Analysis
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall