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Organization

Sungkyunkwan University
Contributors
Talha Ahmed
Yunjong Boo
Gwangeun Byeon
Hyeongjun Cho
Hyungmin Cho
Minkyu Choi
Saeid Gorgin
Seokin Hong
Jisoo Hwang
JOONSEONG HWANG
Yoonho Jang
Minhyeok Jeong
Jungrae Kim
Seongwook Kim
Sihyung Kim
SoYoung Kim
Yoonyoung Kwon
KiHun Ok
Junbum Park
Minjin Park
sanghyeok park
Yesin Ryu
Jaeho Shin
Session Chairs
Yulhwa Kim
Presentations
Engineering Poster
Accelerating Semiconductor Test Data Analysis through CPU-GPU Hybrid Computing: A Resource Optimization Framework
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Networking
Work-in-Progress Poster
Bank-Split PIM: Enabling Concurrent PIM and Memory Operations for LLM Inference in Heterogeneous Systems
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Networking
Work-in-Progress Poster
CiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDs
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Networking
Work-in-Progress Poster
FlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic Array
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
GraphAccel: An In-Storage Accelerator for Efficient Graph-Based Vector Similarity Search Using Page Packing and Speculative Search Optimization
1:45pm - 2:00pm PDT Wednesday, June 25 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Engineering Poster
Networking
HeatSync: Machine Learning-Driven Floorplanning for Optimized Power Integrity and Thermal Integrity in Advanced Packages
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
11:45am - 12:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators
3:45pm - 4:00pm PDT Tuesday, June 24 3003, Level 3
Design
DES4: Digital and Analog Circuits
Networking
Work-in-Progress Poster
ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family Resilient to DPA Attack and Reverse Engineering
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Networking
Work-in-Progress Poster
SafeSSD: Treeless SSD Protection by Leveraging Physical Address as Version Number
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Sessions
Research Manuscript
Everything About LLM and Transformer Accelerators
3:30pm - 5:30pm PDT Tuesday, June 24 3000, Level 3
AI
AI3: AI/ML Architecture Design