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Organization

Advanced Micro Devices (AMD)
Contributors
David Akselrod
Rajesh Anand
Matthew Ballance
Matthew Ballance
Jay Bhadra
Michaela Blott
Alex Branover
Ismail Bustany
Amitabh Das
Monica Farkash
Monica Farkash
Karthik Gedela
Sourabh Goyal
Animesh Jain
Wonjun Jung
Emrah Karagoz
Deepak Kulkarni
Ananth Pallapothu
Rob Pelt
Deepon Saha
Dhruvin Shah
Animesh Sharma
Alex Starr
John Traver
Aniket Waghide
Ferhat Yaman
Session Chairs
Subhajit Dutta Chowdhury
Vidyasagar Ganesan
Wuxi Li
Presentations
Engineering Special Session
A Look into the Future of Verification
1:30pm - 3:00pm PDT Wednesday, June 25 2008, Level 2
Front-End Design
Ancillary Meeting
Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?
12:00pm - 1:30pm PDT Tuesday, June 24 2006, Level 2
Research Special Session
AMD InstinctTM MI300 Series Accelerator: Engineering Showcase of Heterogeneous Integration Technologies
4:30pm - 5:00pm PDT Tuesday, June 24 3010, Level 3
Design
Engineering Presentation
Cross-die timing methodology for Next-Gen Chiplet SOCs - A shift-left solution for cross-foundry 3DIC-STA Signoff
1:30pm - 1:45pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
Networking
Design-for-Verification architecture to shift-left TTM and align test codebase in multi-chiplet SoCs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Tutorial
Emerging Technology Applications on Personalized Edge LLMs
3:30pm - 5:00pm PDT Sunday, June 22 3008, Level 3
AI
Sunday Program
Engineering Special Session
LLM Innovations: Mirage or Milestone ?
1:30pm - 3:00pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Keynote
Michaela Blott
9:00am - 10:00am PDT Tuesday, June 24 3007, Level 3
Engineering Presentation
Refresh your UVM Testbench with a Spritz of Python
10:30am - 10:45am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Ancillary Meeting
Siemens Sponsored: Addressing challenges in software-defined systems electronic development
2:30pm - 3:30pm PDT Tuesday, June 24 2004, Level 2
Ancillary Meeting
Siemens Sponsored: Scaling 3D IC technologies: from niche to mainstream
4:00pm - 5:00pm PDT Tuesday, June 24 2004, Level 2
Engineering Presentation
Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM
10:45am - 11:00am PDT Wednesday, June 25 2010, Level 2
IP
Engineering Special Session
The Evolution of Collaborative Open Source Hardware Development
10:30am - 12:00pm PDT Wednesday, June 25 2012, Level 2
Systems and Software
Sessions
Engineering Presentation
IP Gold – New Digital Design Nuggets
10:30am - 12:00pm PDT Wednesday, June 25 2010, Level 2
IP
Research Manuscript
Smart Circuits, Smarter Algorithms: AI-Driven Innovations in Circuit Modeling and Optimization
10:30am - 12:00pm PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Squeezing Placement from FPGAs, Macros, Down to the Cell Level
10:30am - 12:00pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification