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Organization

Samsung Semiconductor
Contributors
Ayush Agrawal
Sougata Bhattacharjee
Suharini C
Guru Chapi
Himanshu Chauhan
Prasad Dandra
Sekhar Dangudubiyyam
Ratan Deep
Jerin Jose
Sarang Kalbande
Bhargavi Kandala
Sunil Kashide
Naushad Kollikkara
Harshal Kothari
Naga Swetha Maddulapalli
Somraj Mani
Samhith Pottem
Subramanian R
Madhukar Ramegowda
Mohammad Rashid
Thejeswara Reddy
Vasudeva Reddy
Jasobanta Sahoo
Harsh Setia
Harsh Setia
Gulshan Sharma
Omkar Singh
Garima Srivastava
Tushar Vrind
Rinkesh Yadav
Presentations
Engineering Poster
Networking
A Safety Centric approach to Functional Verification of Dual Core Lock-Step Designs
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerated SoC Level Android Home Screen Bring-up, System Software Development and Validation at Pre-Silicon with Advanced Hybrid Emulation Methodology
3:30pm - 3:48pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Poster
Approach For Quality DV Using C2RTL For Algorithmic Designs Authors: Neema Agarwal, Himanshu Chauhan, Harsh Setia, Atharva Mahesh Kakde, Ketki Gosavi
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Enhanced Power Saving with System-on-Chip and Software Design Optimization
3:48pm - 4:06pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Presentation
Expediting UCIe and Boot Verification using Distributed Ndie Simulations and Emulation for Multi-Chiplet AI SoCs
3:45pm - 4:00pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Poster
Networking
Fast-tracking PCIe Verification in an SoC by automating the testbench using triple Check test-suite
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
11:30am - 11:45am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Poster
Networking
Reusable and Efficient Scoreboard Implementation for bug hunting and testbench productivity
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall