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Organization

SK hynix
Contributors
Seungheon Baek
Joohwan Cho
Tei Cho
Wonbeom Choi
Sanghyuk Heo
Yong-Hwan Jeon
Inchul Jeong
Bonggil Kang
Dongkyun Kim
Doyoung Kim
kyeongseob kim
Woongrae Kim
Eunsuk Park
Kyungho Shin
Choungki Song
Presentations
Engineering Poster
AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning
10:30am - 10:45am PDT Monday, June 23 3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Research Manuscript
Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
5:00pm - 5:15pm PDT Wednesday, June 25 3001, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Ancillary Meeting
OpenAccess Coalition Forum: Complimentary Lunch, Sponsored by Si2
1:00pm - 2:45pm PDT Tuesday, June 24 3016, Level 3
Engineering Presentation
Optimal Power Estimation Methodology for CXL Memory Controllers
11:45am - 12:00pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet