Close

Organization

Institute of Computing Technology, Chinese Academy of Sciences
Contributors
Yungang Bao
Lu Chen
Xiaoming Chen
Dongrui Fan
Zheng Feng
Yiming Gan
Chenji Han
Husheng Han
yinhe han
Junying Huang
Zite Jiang
Gao Jun
Huawei Li
Xiaowei Li
Xueqi Li
Zerun Li
Zhichun Li
Cheng Liu
Silin Liu
Zizhen Liu
Hang Lu
Tianrui Ma
Jianan Mu
Penghao Song
Ninghui Sun
Ninghui Sun
Xiaoming SUN
Dingwen Tao
Chongxi Wang
haoxuan wang
Jian Wang
Mingyu Yan
Xiaochun Ye
Haihang You
Zihao Yu
Jinkai Zhang
Lei Zhang
Ran Zhang
Weikang Zhang
Xiaoyu Zhang
Xinyu Zhang
Jiapeng Zhou
Jun Zhou
Shuai Zhou
Presentations
Networking
Work-in-Progress Poster
A Novel Multi-Node-Upset Recoverability Verification Method with Generalized Model for Radiation-Hardened Latches
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
4:15pm - 4:30pm PDT Wednesday, June 25 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
1:30pm - 1:45pm PDT Wednesday, June 25 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
BirdMoE: Reducing Communication Costs for Mixture-of-Experts Training Using Load-Aware Bi-random Quantization
2:45pm - 3:00pm PDT Tuesday, June 24 3000, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
BlockPIM: Optimizing Memory Management for PIM-enabled Long-Context LLM Inference
11:30am - 11:45am PDT Tuesday, June 24 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
CIM-BLAS: Computing-in-Memory Accelerator for BLAS
2:00pm - 2:15pm PDT Wednesday, June 25 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
CXL-Interplay: Unraveling and Characterizing CXL Interference in Modern Computer Systems
3:45pm - 4:00pm PDT Monday, June 23 3001, Level 3
Design
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix Multiplication
3:45pm - 4:00pm PDT Wednesday, June 25 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
2:00pm - 2:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Networking
Work-in-Progress Poster
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
11:30am - 11:45am PDT Wednesday, June 25 3002, Level 3
Security
SEC1: AI/ML Security/Privacy
Research Manuscript
Hypnos: Memory Efficient Homomorphic Processing Unit
4:30pm - 4:45pm PDT Monday, June 23 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Late Breaking Results
Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy Compression
2:30pm - 2:45pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Research Manuscript
MetaDSE: A Few-Shot Meta-Learning Framework for Cross-Workload CPU Design Space Exploration
2:30pm - 2:45pm PDT Wednesday, June 25 3001, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
MOSS: Multi-Modal Representation Learning on Sequential Circuits
11:00am - 11:15am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
5:15pm - 5:30pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
2:15pm - 2:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Research Manuscript
Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
2:15pm - 2:30pm PDT Wednesday, June 25 3008, Level 3
Security
SEC2: Hardware Security: Primitives & Architecture, Design & Test
Research Manuscript
SAPO: Improving the Scalability and Accuracy of Quantum Linear Solver for Portfolio Optimization
1:30pm - 1:45pm PDT Tuesday, June 24 3003, Level 3
Design
DES6: Quantum Computing
Research Manuscript
SIMAX: Accelerating RTL Simulation for Large-Scale Design
4:00pm - 4:15pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Networking
Work-in-Progress Poster
SLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory Irregularity
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
SnapPix: Efficient-Coding--Inspired In-Sensor Compression for Edge Vision
11:30am - 11:45am PDT Tuesday, June 24 3000, Level 3
AI
AI4: AI/ML System and Platform Design