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Organization

Ansys
Contributors
Ahsan Alam
Saeed Asgari
Sai Prabhakar Atluri
Kumar Avala
Naveen B
Harikrishnan Balagopal
Harshul Bansal
Murat Becer
Norman Chang
Jie Cheng
Curtis Clark
Shuoyue Cui
Ed Deeters
Subodh Deodhar
Ansh Dudeja
Maxim Ershov
Johnny Feng
Vineela Gedela
Yongsheng Guo
Henry He
Zhongming Hou
Wei-hsing Huang
Shreyashi Jaiswal
Amit Jangra
Ki Wook Jung
Kopal Kulshreshtha
Myunghoon Lee
Qinglian Li
Yahui Li
Lang Lin
Yiting Lin
Zeqin Lu
Rodger Luo
Sabya Mallick
Sujyesh Aanandh Manjunthan
Dylan McGuire
Maryam Moradpour
Bozidar Novakovic
Chris Ortiz
Vaibhav Rajput
Chidambaram Rakkappan
Roshan Roy
Shreya Sashi
Anush Sharma
Ramesh Sharma
Stuti Singh
Ayush Sood
Garth Sundberg
Ravi Thiruveedhula
Rong Wang
Tao Wang
Xiaodong Wang
Xinying Wang
Zhenbang Wang
Wenbo Xia
Ruoshi Xu
Lucy Yin
Xiaomei You
Ran Zhang
ShuQiang Zhang
Chang Zhao
Li Zou
Session Chairs
T V Narayanan
Presentations
Engineering Poster
A Comprehensive Electromagnetic Analysis Flow for Die and Package Joint Model Simulation of RF Chips Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis
3:30pm - 3:48pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Poster
Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accurate Thermal Simulation of 3DIC Package with Co-Packaged Optics
4:30pm - 4:45pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Engineering Presentation
AI-Driven Multi-Parameters Multi-Objectives Optimization Flow For High-Speed Transmission Line In SerDes Design
11:15am - 11:30am PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
An Efficient Hierarchical Chip-Top Level EMIR Signoff Methodology for Large Automotive SOCs.
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated IR-ECO Flow : Reducing PDN Violations upto 40-50% and Saving Weeks of Engineering Effort
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
10:30am - 10:45am PDT Wednesday, June 25 2010, Level 2
IP
Engineering Poster
Networking
Chip package level thermal integrity analysis of high-power data center chips for hot spot detection
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Comprehensive Power Integrity Analysis of a Super Large Scale 2.5DIC with Multi Silicon Bridges Embedded in Organic Interposer
2:15pm - 2:30pm PDT Monday, June 23 2012, Level 2
AI
Back-End Design
Chiplet
Engineering Presentation
Cost and Compute-efficient IR Drop hierarchical signoff for Subsystem Designs
2:45pm - 3:00pm PDT Monday, June 23 2012, Level 2
AI
Back-End Design
Chiplet
Engineering Poster
Effective Ways of Analyzing and Optimizing Voltage Variation Challenges for 3DIC Chips
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation
11:00am - 11:15am PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Engineering Poster
Networking
From Block, Chip to System - A Comprehensive flow for large FPGA Dynamic Power Integrity Sign-off
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
HeatSync: Machine Learning-Driven Floorplanning for Optimized Power Integrity and Thermal Integrity in Advanced Packages
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Hierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC Structures
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
High-Capacity, High-Performance Chip-Level ESD Analysis for Reliable Semiconductor Designs
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Integrating Self-Heat Analysis in Multiphysics Simulation for Advanced Semiconductor Chip Design
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Machine Learning (ML) Assisted IBIS-AMI Model for Optical Module Involved Advanced SerDes System Designs
10:30am - 10:45am PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Poster
Networking
Machine Learning Based Layout Optimization of Electromagnetic Structures for High-Speed IO Design
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Mitigating Routing Congestion in Automotive SoCs with ML based Power Grid Optimization
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Novel IC layout parasitics analysis techniques to enhance Custom Macro/IP and Standard cell library development flow
4:00pm - 4:15pm PDT Monday, June 23 2010, Level 2
IP
Engineering Poster
Novel Shift-Left Methodology for System Power Integrity Analysis with Early Chip Power Model
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
On-Die Power Noise impact on High-Speed Signal Integrity (SI) of Photonics computing chip base on 3D Heterogeneous Integration
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Power-aware DFT-driven High Confidence EMIR Signoff for Low Power Automotive SoCs
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Reducing High di/dt Simultaneous Switching Noise in Advanced Multiprocessor SoCs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
SigmaAV: High Global and Local Noise Coverage Solution for Power Integrity Signoff
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Sign-off Challenges and Solutions in Power Integrity and Reliability Analysis of 2.5DIC Silicon Interposer
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
Top 3D-IC Innovators Tackle Multiphysics Challenges in Multi-Die Silicon Design
4:15pm - 5:15pm PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Presentation
Unveiling the Core Truth: Advanced Glitch Power Analysis and Optimization Using Statistical Methodology
11:15am - 11:30am PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Sessions
Research Manuscript
Exploring the Unchartered: From Chiplets to Architecture and Validation
3:30pm - 5:30pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package