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Organization

Nvidia
Contributors
Ramesh Agarwal
Anthony Agnesina
Yunsheng Bai
Emmanuel Chao
Steve Dai
Chenhui Deng
Mike Garrett
Mark Ho
Eric Hsu
Ben Keller
Brucek Khailany
Jin-Sung Kim
Kishor Kunal
Rongjian Liang
Rongjian Liang
Dr. John Linford
Danny Liu
Wen-Hao Liu
Yi-Chen Lu
Ying Luo
Vikram Sharma Mailthody
Vishal Malik
Haoxing Ren
Santosh Santosh
Pratik Shah
Rajvi Shah
Syed Suhaib
Michael Sullivan
Preetika Tandon
Anusha Vemuri
Rangharajan Venkatesan
Stephen Wang
John Wilson
Haoyu Yang
Yanqing Zhang
Session Chairs
Chenhui Deng
Yonggan Fu
Abhinav Goel
Johannes Maximilian Kuehn
Kishor Kunal
Shiyu Li
Marina Neseem
Haoxing “Mark” Ren
Presentations
Research Special Session
Accelerated Quantum Supercomputing
2:00pm - 2:30pm PDT Monday, June 23 3010, Level 3
Design
Ancillary Meeting
Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?
12:00pm - 1:30pm PDT Tuesday, June 24 2006, Level 2
Engineering Poster
Networking
An Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Panel
Beyond Limits: Packaging, Cryogenic, and New Cooling Strategies for Future Computing
10:30am - 12:00pm PDT Tuesday, June 24 3012, Level 3
Systems
Research Manuscript
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
2:45pm - 3:00pm PDT Monday, June 23 3000, Level 3
AI
AI1: AI/ML Algorithms
Research Panel
Chips and Systems for AI: Gains, Drains and the Uncharted Road Ahead
10:30am - 12:00pm PDT Wednesday, June 25 3012, Level 3
AI
Research Manuscript
CirSTAG: Circuit Stability Analysis on Graph-based Manifolds*
10:45am - 11:00am PDT Monday, June 23 3000, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
DCO-3D: Differentiable Congestion Optimization in 3D ICs
1:45pm - 2:00pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Workshop
First International Workshop on Synergizing AI and Circuit-System Simulation
1:30pm - 5:00pm PDT Sunday, June 22 3003, Level 3
AI
Sunday Program
Research Manuscript
GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
2:15pm - 2:30pm PDT Wednesday, June 25 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
GEM: GPU-Accelerated Emulator-Inspired RTL Simulation*
4:30pm - 4:45pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
Generalizable Lithographic Hotspot Detection Using Asynchronous Meta-Learning with Only One Shot
2:15pm - 2:30pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Engineering Poster
Networking
HBM Timing Methodology with Liberty LVF
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications*
10:30am - 10:45am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Late Breaking Results
Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Presentation
Novel Clocks and Resets Architecture Model
2:15pm - 2:30pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Research Manuscript
PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators
3:45pm - 4:00pm PDT Tuesday, June 24 3003, Level 3
Design
DES4: Digital and Analog Circuits
Research Manuscript
Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing
2:15pm - 2:30pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
ReVEAL: Reverse Engineering of Multiplier Architectures via Graph Learning for Computer Algebra Verification
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Poster
Networking
SigmaAV: High Global and Local Noise Coverage Solution for Power Integrity Signoff
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity
4:30pm - 4:45pm PDT Tuesday, June 24 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model Training
2:00pm - 2:15pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Engineering Poster
Networking
Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
TechTalk
Unlocking the Power of AI in EDA
11:15am - 12:00pm PDT Monday, June 23 DAC Pavilion, Level 2 Exhibit Hall
Sessions
Research Manuscript
Transformers: Rise of the Optimized Large Language Models
1:30pm - 3:00pm PDT Monday, June 23 3001, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
Smarter Systems: The Future of Hardware Efficiency in AI
10:30am - 12:00pm PDT Tuesday, June 24 3001, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
LLM Uprising: Fast & Furious
1:30pm - 3:00pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Research Manuscript
The ‘Auto’ in Autonomous Systems
1:30pm - 3:00pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS1: Autonomous Systems (Automotive, Robotics, Drones)
Engineering Presentation
AI and Chiplet/Multi-die: Verification Scalability and AI driven Automation
3:30pm - 5:00pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Research Manuscript
Breakthroughs in VLSI: Power-Efficient AI and Revolutionary Circuitry
3:30pm - 5:30pm PDT Tuesday, June 24 3003, Level 3
Design
DES4: Digital and Analog Circuits
Research Manuscript
Flattering Splatting: Gaussian Splatting, Video Processing, and Diffusion
1:30pm - 3:00pm PDT Wednesday, June 25 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
We HAS to Have These HARDWARE ACCELERATOR SYSTEMS for Deep Learning!
1:30pm - 3:00pm PDT Wednesday, June 25 3001, Level 3
AI
AI3: AI/ML Architecture Design