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Organization

Siemens
Contributors
Farhard Ahmed
Kamal Ait-chergui
Ajaj Ansari
Mohamed Atoua
Hadar Baran
Divya Bareja
Soufian Bouazizi
Sunsoo Byun
Ouidiane CHAFIK
Amit Dey
Geir Eide
Yousry ElMaghraby
Mohammed Fahad
John Ferguson
Tom Fitzpatrick
Harry Foster
Harry Foster
David Fritz
Anmol Garg
Andreas Glowatz
Amit Gupta
Amit Gupta
Ankur Gupta
Sanchita Gupta
Sarah Hesham
ANBAR hicham
Lih-Jen Hou
Joe Hupcey
AJ Incorvaia
Kyunghan Kang
Vishnu Kanwar
Mathilde Karsenti
Vishal Kashyap
Ivan Kissiov
Abhi Kolpekwar
Abhi Kolpekwar
Kevin Krieger
Ajay Kumar
Manish Kumar
Heng Lan Lau
Seunghyun Lee
Sungyoun Lee
Ling Lei
Yuling Lin
Mohamed Moselhy
Abdul Moyeen
Michael Munsey
Mohamed Nafea
Faheem Ahmed Qazi
Shravan Ramesh
Waseem Raslan
Juan Rey
Cooper Robertson
Youssef Saroukh
GAZAL SINGLA
Vijay Tayal
Shane Toma
Ray Valencia
Cameron Villone
Salma Youssef
Dan Yu
Session Chairs
Kai-Yuan (Kevin) Chao
David Chinnery
Dave Rich
Presentations
Engineering Poster
A Novel Solution for Parasitic resistance analysis: Calibre PERC-Driven Optimization for PEX Quality Assurance
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology
11:00am - 11:15am PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
Networking
Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerating SRAM Design Cycles With Additive AI Technology
10:30am - 10:45am PDT Monday, June 23 2010, Level 2
AI
IP
Ancillary Meeting
Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?
12:00pm - 1:30pm PDT Tuesday, June 24 2006, Level 2
Engineering Presentation
Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations
11:45am - 12:00pm PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
Networking
Advanced Yield Prediction for SRAM Bitcells with Rare Defect Modeling Leveraging AI-Powered Methodology
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated AI-ML based flow for Validated Constraint Generation for CDC/RDC
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated QA for Standard Cell Libraries used in RAIN RFID Chips
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
Beyond Breaking the Bottleneck: Smart Verification for Modern Complexity
12:00pm - 12:30pm PDT Monday, June 23 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Special Session
CDC-RDC Inter-operable Collateral Standardization
10:30am - 12:00pm PDT Monday, June 23 2008, Level 2
Back-End Design
Engineering Poster
Chip reliability with antenna discharge path consideration
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
Engineering the Semiconductor Digital Thread
12:00pm - 12:30pm PDT Wednesday, June 25 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Poster
Networking
Enhanced LVS Techniques for Fast Convergence and Optimized Design Cycles
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Enhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros/IP and Standard Cell Libraries
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Tutorial
Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators Using HLS4ML
1:30pm - 3:00pm PDT Sunday, June 22 3008, Level 3
AI
Sunday Program
Engineering Presentation
Fear Not! With LLMs, Learning PSS Isn't Scary At All
4:45pm - 5:00pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
DAC Pavilion Panel
Generative AI in Design & Verification: Are We Hallucinating or Innovating?
2:00pm - 2:45pm PDT Monday, June 23 DAC Pavilion, Level 2 Exhibit Hall
Research Panel
Generative AI in Electronic Design Automation (EDA): Revolution or Risk?
1:30pm - 3:00pm PDT Wednesday, June 25 3012, Level 3
AI
EDA
Engineering Poster
Networking
Innovative and Cost-Effective Approach to ESD Reliability Verification in the Cloud
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Innovative RDL PEX flow with Calibre, enhances design reliability and performance
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
IP-Report: Methodology to Identify Simple Yet Effective Module Based Power Saving Techniques
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
Leveraging AI to Boost Productivity and Quality of Results in the Digital Design Creation Flow
12:00pm - 12:30pm PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Special Session
LLM Innovations: Mirage or Milestone ?
1:30pm - 3:00pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Presentation
Logic and SRAM Library Generation and Analysis for Digital Design Enablement
3:45pm - 4:00pm PDT Monday, June 23 2010, Level 2
IP
Engineering Presentation
Novel TRNG Verification with a High-Performance Simulation Methodology
10:45am - 11:00am PDT Monday, June 23 2010, Level 2
AI
IP
Engineering Poster
Peak Power Optimization in RTL2GDS flow using guidance from RTL Power Optimization tools
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Portfolio Re-characterization using AI
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Robust Verification for Complex Liberty IP
4:45pm - 5:00pm PDT Monday, June 23 2010, Level 2
IP
Ancillary Meeting
Siemens Sponsored: Achieving industrial-grade AI in EDA: challenges, lessons, and opportunities
4:30pm - 5:15pm PDT Monday, June 23 2004, Level 2
Ancillary Meeting
Siemens Sponsored: Addressing challenges in software-defined systems electronic development
2:30pm - 3:30pm PDT Tuesday, June 24 2004, Level 2
Engineering Special Session
SLM Is the New DFT – Are You Ready?
3:30pm - 5:00pm PDT Monday, June 23 2012, Level 2
Back-End Design
TechTalk
Unlocking the Power of AI in EDA
11:15am - 12:00pm PDT Monday, June 23 DAC Pavilion, Level 2 Exhibit Hall
Engineering Poster
Networking
Using AI to validate standard cell Liberty IP riddled with sparse and disparate data
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Sessions
Research Manuscript
Navigating the Frontiers of Neural Networks
10:30am - 12:00pm PDT Tuesday, June 24 3000, Level 3
AI
AI4: AI/ML System and Platform Design
Engineering Presentation
Verification Innovation: Shaping the Future of Design Validation
10:30am - 12:00pm PDT Wednesday, June 25 2008, Level 2
Front-End Design
Research Manuscript
Navigating 3D, Clock Trees, and Shared Learning
1:30pm - 3:00pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification