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Organization

IBM Research
Contributors
Tyler Baldwin
David Beymer
Jennifer Kazda
Charles Mackin
Vandana Mukherjee
Wachirawit Ponghiran
Lakshmi Reddy
Luyao Shi
Prashanth Vijayaraghavan
Presentations
Networking
Work-in-Progress Poster
CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Poster
Networking
Design Optimization of ASIC Designs via AI-driven RTL-to-GDS Optimization with Floorplanning
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Presentation
Routing Congestion Mitigation Techniques Targeting Dense Designs
2:00pm - 2:15pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Networking
Work-in-Progress Poster
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby