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Organization

Institute of Microelectronics, Chinese Academy of Sciences
Contributors
He Cao
Rui Chen
Chunmeng Dou
Xiangqu Fu
Hanghang Gao
Xin Hong
Hongyang Hu
Ziyi Hu
Yujie Jiang
Ling Li
Zhiqiang Li
Jianyun Liu
Xiaoning Ma
Shushan Qiao
Pengyu Ren
Dashan Shang
Xiaojing Su
Yajuan Su
Zeyu Sun
Weijie Tong
Yuqin Wang
Yayi Wei
Yuanlu Xie
Qinzhi Xu
Xiaoxin Xu
Jianguo Yang
Zhenjie Yao
Jinshan Yue
Feng Zhang
Haiyang Zhou
Presentations
Research Manuscript
An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering
2:30pm - 2:45pm PDT Monday, June 23 3001, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
ChipletEM: Physics-Based 2.5D and 3D Chiplet Integration Electromigration Signoff Tool Using Coupled Stress and Thermal Simulation
11:45am - 12:00pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory
11:00am - 11:15am PDT Tuesday, June 24 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Networking
Work-in-Progress Poster
Generator of constrained test pattern based on multi-scale gradient generative adversarial networks
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
11:30am - 11:45am PDT Wednesday, June 25 3002, Level 3
Security
SEC1: AI/ML Security/Privacy
Networking
Work-in-Progress Poster
MPE : A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression Scheme
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Re4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
2:15pm - 2:30pm PDT Wednesday, June 25 3008, Level 3
Security
SEC2: Hardware Security: Primitives & Architecture, Design & Test
Networking
Work-in-Progress Poster
Self-Supervised Learning based Etching Process Modeling: Bridging Simulation and Experimental Data
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby