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Organization

Hong Kong University of Science and Technology (HKUST), Guangzhou
Contributors
Chen Chen
Xinyu Chen
Shanshi Huang
Zijun JIANG
Yangdi Lyu
Xiangchen Meng
Yikang Ouyang
Yan TAN
Jiang Xu
Hongce Zhang
Presentations
Research Manuscript
An Efficient Compute-in-Memory based Accelerator for Point-based Point Cloud Neural Networks
4:45pm - 5:00pm PDT Tuesday, June 24 3001, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme
11:45am - 12:00pm PDT Tuesday, June 24 3008, Level 3
Security
SEC4: Embedded and Cross-Layer Security
Research Manuscript
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
2:00pm - 2:15pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
3:45pm - 4:00pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
Efficient Continuous Logic Optimization with Diffusion Model
11:15am - 11:30am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
2:00pm - 2:15pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure