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Organization

University of California, Berkeley
Contributors
Bora Nikolic
Pierluigi Nuzzo
Hang Ren
Alberto Sangiovanni-Vincentelli
Tianshi Wang
Presentations
Networking
Work-in-Progress Poster
Automated Hardware-Mapping Co-Design for Neural Network Acceleration with Single-Step Reinforcement Learning
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Panel
Chips and Systems for AI: Gains, Drains and the Uncharted Road Ahead
10:30am - 12:00pm PDT Wednesday, June 25 3012, Level 3
AI
Research Manuscript
EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits
1:30pm - 1:45pm PDT Monday, June 23 3003, Level 3
Design
DES6: Quantum Computing
Research Manuscript
G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
11:15am - 11:30am PDT Monday, June 23 3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Ancillary Meeting
IEEE Council on EDA Distinguished Panel - 20th Anniversary Panel: AI Hardware & EDA, the next 20 years: Smarter, Taller, Deeper
12:00pm - 1:30pm PDT Tuesday, June 24 3016 & 3018