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Organization

National Taiwan University
Contributors
Zong-Ying Cai
Che-Ming Chang
Hsin-Tzu Chang
Yao-Wen Chang
Hsin-Yu Chen
Liang-Chi Chen
Min-Hung Chen
Shao-Hsiang Chen
Yan-Jen Chen
Yen-Ting Chen
Zheng-Wei Chen
Ting-Hsun Chi
Cheng-Yu Chiang
Hao-Wei Chiang
Kai-Hsiang Chiu
Shiuan-Yun Ding
Yang Hsu
Chih-Yu Hu
Chi-Tse Huang
Chung-Yang (Ric) Huang
Wei-Kai Huang
Iris Hui-Ru Jiang
Tei-Wei Kuo
Chao-Chi Lan
Mu-Te Lau
Zhu-Xun Lee
Cheng-Yen Li
Cheng-Yen Li
Jun-Wei Liang
Shao-Yu Lo
Chiao-Yu Ou
Chuan-Chi Su
Chuan-Chi Su
Chung-Ting Tsai
Chien-Hao Tsou
Tzu-Yu Tung
Jen-Chieh Wang
An-Yeu (Andy) Wu
Hao-Yu Wu
Hsiang-Chun Yang
Presentations
Networking
Work-in-Progress Poster
Analytical Warpage-aware Multi-die Floorplanning for Advanced Package Designs
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
Blaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum Circuits
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Clearance-Constrained PCB Global Placement with Heterogeneous Components
10:30am - 10:45am PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-Oriented Components
10:45am - 11:00am PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based Filtering
3:30pm - 3:45pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Research Manuscript
Easz: An Agile Transformer-based Image Compression Framework for Resource-constrained IoTs
3:45pm - 4:00pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies
Research Manuscript
Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation
3:30pm - 3:45pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
Energy-Efficient Large-Scale Vector Similarity Search in NAND-Flash via Hybrid Matching
1:45pm - 2:00pm PDT Monday, June 23 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Networking
Work-in-Progress Poster
Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Generative Model Based Standard Cell Timing Library Characterization
11:00am - 11:15am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Research Manuscript
Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer Partition
5:15pm - 5:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Late Breaking Results
Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Late Breaking Results
Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Late Breaking Results
Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze Routing
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Late Breaking Results
Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
4:30pm - 4:45pm PDT Tuesday, June 24 3001, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Networking
Work-in-Progress Poster
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Segmented Angular Pre-Processing for Accurate and Efficient In-Memory Vector Similarity Search
2:15pm - 2:30pm PDT Wednesday, June 25 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Networking
Work-in-Progress Poster
Unleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack Memories
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby