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Organization

National University of Defense Technology
Contributors
Liu Biwei
Yonggang Che
Yingwen Chen
Yiqin Dai
Yan Ding
Yue Ding
Pan Dong
Zhenling Duan
Jianbin Fang
Xiaoxiang Fang
Wenwen Fu
Zhimeng Han
Renshuang Jiang
Xuyan Jiang
Zhu Junyi
Dongsheng Li
Hanqing Li
Shen Li
Shengguo Li
Tiejun Li
Tiejun Lie
Jie Liu
Shengbai Luo
Jun Ma
Sheng Ma
Sheng Ma
Linbo Qiao
Lang Qingjie
Haozhong Qiu
Wang Ruoxi
Luo shengbai
Yihao Shi
Yu Shi
Zhigang Sun
Jixuan Tang
Yu Tang
Yuhan Tang
Bo Wang
Yue Wang
Lizhou Wu
Chuanfu Xu
Qingshan Xue
Xiangrui Yang
Lujia Yin
Xu Yongjian
Jianmin Zhang
Xueyi Zhang
Yunping Zhao
Xiaofeng Zou
Presentations
Networking
Work-in-Progress Poster
ADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient Merging
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
An Innovative Memory Design with Internal ECC Functionality Based on In-Memory Computing
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
DSPlacer: DSP Placement for FPGA-based CNN accelerator
10:30am - 10:45am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
4:30pm - 4:45pm PDT Wednesday, June 25 3008, Level 3
Systems
SYS6: Time-Critical and Fault-Tolerant System Design
Networking
Work-in-Progress Poster
HeadTile: A Scalable and Efficient Accelerator for Large Language Model Inference with 3D Memory Integration
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
2:00pm - 2:15pm PDT Monday, June 23 3008, Level 3
Systems
SYS5: Embedded Memory and Storage Systems
Networking
Work-in-Progress Poster
LLM-based Soft Error tolerant Design for DNN accelerators
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Me-MPK: Accelerating Krylov Subspace Solvers via Memory-efficient Matrix-Power Kernel
1:45pm - 2:00pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Research Manuscript
Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
4:00pm - 4:15pm PDT Wednesday, June 25 3008, Level 3
Systems
SYS6: Time-Critical and Fault-Tolerant System Design
Networking
Work-in-Progress Poster
SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Networking
Work-in-Progress Poster
TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
4:15pm - 4:30pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS3: Embedded Software