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Organization

The Chinese University of Hong Kong, Shenzhen
Contributors
Tinghuan Chen
Zhiyuan Lu
Yuan Pu
Tongkai Wu
Baohui Xie
Bei Yu
Xinrui Zhu
Presentations
Research Manuscript
DSPlacer: DSP Placement for FPGA-based CNN accelerator
10:30am - 10:45am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
Efficient Continuous Logic Optimization with Diffusion Model
11:15am - 11:30am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
5:15pm - 5:30pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
4:00pm - 4:15pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Research Manuscript
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
5:00pm - 5:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
11:15am - 11:30am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization