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Organization

Synopsys
Contributors
Jaskaran Ajimal
Luca Amaru
Vishal Aralikatti
Ricardo Araujo
Sachin Bansal
suresh barla
Mohita Batra
Massimo Bertoletti
Vikram Bhatia
Patrick Blestel
Mara Carvalho
Wei-Ting Chan
Alex Chang
Tung-Chieh Chen
Luis Cruz
Sabya Das
Celso Figueiredo
Luis Francisco
Vaibhav Garg
Manish Goel
Amit Goldie
Badri Gopalan
Deyuan Guo
Len Hsu
Himanshu Kathuria
Vishal Keswani
Abhishek Kumar
Sudipto Kundu
Zhaojie Li
Min-Ching Lin
Brian Lockyear
Srinivasulu M
Paulo Magno
Pawini Mahajan
BHAVANA MALLIKARJUNAIAH
Mohan Mangal
Giulia Meuli
Ankit Narang
Sashi Obilisetty
Sridhar Panchapakesan
Steve Pateras
Tanuja Rao
Tanuja Rao
M.Vaishnavi Reddy
Sean Safarpour
Arjun Saha
Rakesh Shenoy
Wei-Kai Shih
Rishabh Srivastava
Fengfeng Tang
Elena Teica
Domingos Terra
Eleonora Testa
Benson Tsao
Alan Vaz
Joddy Wang
Zhuo Wang
Dehuang Wu
Vinson Wu
Kai-Chuan Yang
Jian Yu
Wei Zeng
Yervant Zorian
Session Chairs
Luigi Capodieci
Sabya Das
Igor Markov
Frank Schirrmeister
Eleonora Testa
Presentations
Engineering Presentation
A Leap Forward in Formal Verification Using Generative AI
4:15pm - 4:30pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Poster
Networking
A Solution for intermittently and Fastly Power On Repair
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation
11:45am - 12:00pm PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Exhibitor Forum
Accelerating Tapeout by Months with Cost-Effective Per-Minute EDA Cloud Licensing
3:30pm - 4:00pm PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Ancillary Meeting
Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?
12:00pm - 1:30pm PDT Tuesday, June 24 2006, Level 2
Engineering Presentation
AI-aided flow for digital verification of a multiprotocol SerDes PHY
2:45pm - 3:00pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
Networking
Automated IR convergence with PrimeClosure IR-ECO
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated IR-ECO Flow : Reducing PDN Violations upto 40-50% and Saving Weeks of Engineering Effort
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
Boolean Reasoning Guided Ungrouping
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Poster
Networking
Boosting Low Power Verification Methodology: Introducing Power-Aware Formal Property Verification into the Flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Detection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS)
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Special Session
Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
1:30pm - 3:00pm PDT Monday, June 23 2008, Level 2
AI
Back-End Design
Chiplet
Research Manuscript
Generative Model Based Standard Cell Timing Library Characterization
11:00am - 11:15am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Engineering Poster
Networking
Improving Digital Design performance and area using DSO.ai
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design Insights
11:15am - 11:30am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Engineering Special Session
Keeping the Guard Up with Security across the Board
1:30pm - 3:00pm PDT Wednesday, June 25 2010, Level 2
Back-End Design
Late Breaking Results
Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Poster
Networking
Leveraging Machine Learning to Automate Waiver Generation for Static Lint Violations
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Methodology to Generate Synthesis Signoff Quality Optimized Registers at RTL and Application of Generated Optimized Registers into RTL and Implementation Design Flows to Improve Productivity
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Special Session
Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem
10:30am - 12:00pm PDT Monday, June 23 2012, Level 2
Front-End Design
Chiplet
Research Panel
Performance vs. Sustainability: The Challenge of Energy-Efficient Computing
1:30pm - 3:00pm PDT Monday, June 23 3012, Level 3
Systems
Engineering Presentation
Revolutionizing Digital ASIC Design through AI
4:00pm - 4:15pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Presentation
Robust Hard Macro Timing Validation: Early Detection of Issues and Automated Feedback for Integration
4:30pm - 4:45pm PDT Monday, June 23 2010, Level 2
IP
Research Manuscript
Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
11:45am - 12:00pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Engineering Special Session
SLM Is the New DFT – Are You Ready?
3:30pm - 5:00pm PDT Monday, June 23 2012, Level 2
Back-End Design
Engineering Presentation
UPF Guided Design Editing for Early Low Power Verification Sign Off
10:45am - 11:00am PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Sessions
Research Special Session
Large Language Model - the "Current Big Thing" in the Semiconductor World
10:30am - 12:00pm PDT Monday, June 23 3010, Level 3
AI
Research Manuscript
From Pixels to Chips: AI-Enhanced Layout & Mask Design
1:30pm - 3:00pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Engineering Presentation
Back-end and System Considerations for Chiplets
3:30pm - 5:00pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Research Manuscript
Follow the Logic: Advances in Logic Synthesis
3:30pm - 5:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
Navigating 3D, Clock Trees, and Shared Learning
1:30pm - 3:00pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification