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Organization

University of Science and Technology of China
Contributors
Hong An
Junshi Chen
Lin Chen
Song Chen
Yeqiu Chen
Qianyu Cheng
Hu Ding
Huanshuo Dong
Wei Fu
Zijie Geng
Lei Gong
Xiaoyu Hao
Yi-Xiang Hu
Qiming Huang
Zhen Huang
JiaJun Ji
Weiqing Ji
Yunjie Ji
Qingcai Jiang
Yier Jin
Yi Kang
Mingyang Kou
Cheng Li
Jinao Li
Shijie Li
Xi Li
Ziyan Liu
Yuxi Qian
Yunji Qin
Zhihao Shi
Zijia Su
Guowei Sun
Cheng Tang
Buxin Tu
Zhaojie Tu
Chao Wang
Chengkai Wang
hong wang
Hong Wang
Jie Wang
Teng Wang
Xianglu Wang
Zhihai Wang
Zihan Wang
Hongbing Wen
Di Wu
Feng Wu
Qi Xu
Zhexuan Xu
Yuxuan Yang
Hailong Yao
Chenming Zhang
Yu Zhang
Yifang Zhao
Zhendong Zheng
Kexin Zhou
Xuehai Zhou
Xuehai Zhou
Presentations
Networking
Work-in-Progress Poster
Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
5:15pm - 5:30pm PDT Wednesday, June 25 3000, Level 3
AI
AI3: AI/ML Architecture Design
Networking
Work-in-Progress Poster
Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
3:45pm - 4:00pm PDT Monday, June 23 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Networking
Work-in-Progress Poster
FuncFormer: Circuit Representation Learning via the Flow of Functional Propagation
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
4:45pm - 5:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Networking
Work-in-Progress Poster
HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
1:45pm - 2:00pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure
Networking
Work-in-Progress Poster
Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Late Breaking Results
Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Late Breaking Results
Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
4:00pm - 4:15pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Research Manuscript
Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
2:30pm - 2:45pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing System
5:00pm - 5:15pm PDT Tuesday, June 24 3001, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
PatLabor: Pareto Optimization of Timing-Driven Routing Trees
1:30pm - 1:45pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
PECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAs
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Networking
Work-in-Progress Poster
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Networking
Work-in-Progress Poster
PPA-driven Placement via Adaptive Cluster Constraints Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Self-Attention To Operator Learning-based 3D-IC Thermal Simulation
11:30am - 11:45am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
To Tackle Cost-Skew Tradeoff: An Adaptive Learning Approach for Hub Node Selection
2:30pm - 2:45pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning Framework
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
TSO: Boosting Rematerialization Training via Optimal Tensor Scheduling Optimization
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
4:00pm - 4:15pm PDT Wednesday, June 25 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
11:00am - 11:15am PDT Tuesday, June 24 3003, Level 3
Design
DES2A: In-memory and Near-memory Computing Circuits