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Organization

The Chinese University of Hong Kong
Contributors
Zelin Du
Rongliang Fu
Zhuolun He
Tsung-Yi Ho
Kecheng HUANG
Zixuan HUANG
Shui Jiang
Sadaf Khan
Chengxi Li
Siyuan Liang
Peiyu Liao
Dahua Lin
Hongduo Liu
Tianji Liu
Yi Liu
Yuan Pu
Zili Shao
Zhengyuan Shi
Yang Sun
Tiebing Tang
Yingjia Wang
Zixiao WANG
Martin Wong
Haoyuan WU
Changran Xu
Peng Xu
Qiang Xu
Ming-Chang Yang
Yuyang Ye
Shuo Yin
Evangeline Young
Bei Yu
Ziyang Yu
Yuxuan Zhao
Su Zheng
Ziyang Zheng
Yunhao Zhou
Jiaying Zhu
Zhen Zhuang
Presentations
Research Manuscript
3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
1:30pm - 1:45pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
2:15pm - 2:30pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
5:15pm - 5:30pm PDT Monday, June 23 3003, Level 3
Design
DES3: Emerging Models of ComputatioN
Research Manuscript
ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script Customization
10:30am - 10:45am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
Curvilinear Optical Proximity Correction via Cardinal Spline
2:45pm - 3:00pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs
2:30pm - 2:45pm PDT Monday, June 23 3008, Level 3
Systems
SYS5: Embedded Memory and Storage Systems
Research Manuscript
From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
5:00pm - 5:15pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing
2:00pm - 2:15pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Networking
Work-in-Progress Poster
HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
iG-kway: Incremental k-way Graph Partitioning on GPU
3:30pm - 3:45pm PDT Wednesday, June 25 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Late Breaking Results
Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
1:45pm - 2:00pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Research Manuscript
Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
5:00pm - 5:15pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization*
1:30pm - 1:45pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
MOSS: Multi-Modal Representation Learning on Sequential Circuits
11:00am - 11:15am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
5:00pm - 5:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
11:30am - 11:45am PDT Wednesday, June 25 3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
11:15am - 11:30am PDT Wednesday, June 25 3002, Level 3
Security
SEC1: AI/ML Security/Privacy
Research Manuscript
Simulation-based Parallel Sweeping: A New Perspective on Combinational Equivalence Checking
4:45pm - 5:00pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Research Manuscript
smaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
11:30am - 11:45am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
Speculative Decoding for Verilog: Speed and Quality, All in One
10:30am - 10:45am PDT Tuesday, June 24 3001, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction
4:30pm - 4:45pm PDT Wednesday, June 25 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
The Unwritten Contract of Cloud-based Elastic Solid-State Drives
10:45am - 11:00am PDT Wednesday, June 25 3008, Level 3
Systems
SYS5: Embedded Memory and Storage Systems
Research Manuscript
Tropical: Enhancing SLO Attainment in Disaggregated LLM Serving via SLO-Aware Multiplexing
5:15pm - 5:30pm PDT Monday, June 23 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
11:15am - 11:30am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization