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Organization

IBM
Contributors
Margaret Allen
Robert Allen
Rich Carbone
Ajith Chandrasekaran
Bijian Chen
Utkarsh Chitransh
Dan Coops
Santanu Das
Ehsan Degan
Mitch DeHond
Nagu Dhanwada
Nagu Dhanwada
Jack DiLullo
Derren Dunn
Derren Dunn
Ali El-Zein
Eric Foreman
Aryan Garg
Charles Gates
Hemlata Gupta
Nidhi Gupta
Sachin Gupta
Matt Guzowski
Arvind Haran
Nathaniel Hieter
Ashutosh Jadhav
Samvedna Jha
Gireesh kumar K M
Kerim Kalafala
Steven Kurtz
Lan Luo
Bria Matthews
Prabhat Maurya
Michael Monkowski
Haritha Mudimela
Vandana Mukherjee
Apoorva Nitsure
Nayo Ogilvie
Viresh Paruthi
Robert Perricone
Nitin Pundir
Ashish Ranjan
Nanditha Rao
Rahul Rao
Shruthi Ravindra
Ron Rose
Maya Safieddine
Michael Sitko
Alex Suess
Akil Sutton
Chakradhar Thallapaka
Rafael Toche Pizano
Hsinyu Tsai
Sanjay Upreti
Manish Verma
Richard Wachnik
Frank Wallingford
David Winston
Indramani Yadav
Xin Zhang
Xin Zhao
nancy Zhou
Session Chairs
Michael Kazda
Xin Zhao
Presentations
Engineering Poster
Networking
Agentic AI Approach to Optimize Front-End EDA Tools Flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Research Special Session
Architecture and Design Approaches towards Large-scale AI Hardware Acceleration
11:00am - 11:30am PDT Tuesday, June 24 3010, Level 3
AI
Networking
Work-in-Progress Poster
CIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL Refinement
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Engineering Poster
Networking
Design Optimization of ASIC Designs via AI-driven RTL-to-GDS Optimization with Floorplanning
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Exhibitor Forum
EDA as a Solution: enabling world class dynamic design and foundry facing workflows
1:45pm - 2:15pm PDT Wednesday, June 25 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Poster
Efficient Translation of OpenAccess Design Data to the OASIS® Format
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Networking
Work-in-Progress Poster
Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Engineering Poster
Networking
Exploring the Latent Space in a Variational Auto Encoder when Addressing Local Layout Effects
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Ancillary Meeting
IEEE 2416 System Power Modeling Working Group Open Meeting: Sponsored by Si2
10:00am - 11:30am PDT Tuesday, June 24 3014, Level 3
Networking
Work-in-Progress Poster
LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Engineering Poster
Networking
Method of Constraint Transformation in Static Timing Analysis for Dual Edge Timing
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Method of Static Timing Analysis for Dual Edge Triggered Pulsed Latches
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Ancillary Meeting
Powering the Future of AI: Are Standards an Enabler or a Bottleneck?: Panel with Complimentary Lunch, Sponsored by Si2
12:00pm - 1:00pm PDT Tuesday, June 24 3014, Level 3
Tutorial
Powering the Future: Mastering IEEE 2416 System Level Power Modeling Standard for Low-Power AI and Beyond
9:00am - 12:30pm PDT Sunday, June 22 3008, Level 3
AI
Sunday Program
Engineering Poster
Networking
Pre-Validation Tool: Minimizing Errors, Maximizing Efficiency
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Recalibration of MOSFET Compact Models based on Complex Product-Related Layouts using Bayesian Optimization
10:45am - 11:00am PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Presentation
Reconfigurable Vector Floating Point Accelerator on FPGAs
11:45am - 12:00pm PDT Wednesday, June 25 2010, Level 2
IP
Engineering Presentation
Routing Congestion Mitigation Techniques Targeting Dense Designs
2:00pm - 2:15pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Networking
Work-in-Progress Poster
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
DES5: Emerging Device and Interconnect Technologies
Engineering Poster
Networking
Single Corner Mixed Voltage Functional Noise Analysis
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Timing Visualizer AI Assistant: A Novel Machine Learning Application for Efficient Timing Triage
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Front-End Design
Sessions
Research Manuscript
Breakthroughs in Timing Prediction, Analysis, and Optimization
10:30am - 12:00pm PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Research Manuscript
All You Can Route Buffet
1:30pm - 3:00pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA7: Physical Design and Verification