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Organization

State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences
Contributors
Zhiteng Chao
Mingyu Chen
Shijian Chen
Shuo Chen
Huimin Cui
Xiaobing Feng
Meng Gao
Feng Gu
Shengwen Liang
Zeshi Liu
Bin Sun
Mingjun Wang
Ziheng Xiao
Biwei Xie
Runzhen Xue
yinghao yang
Haihang You
Xinmiao Zhang
Jiacheng Zhao
Presentations
Research Manuscript
A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction
11:30am - 11:45am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Research Manuscript
Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
1:30pm - 1:45pm PDT Wednesday, June 25 3002, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
2:00pm - 2:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Networking
Work-in-Progress Poster
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Hypnos: Memory Efficient Homomorphic Processing Unit
4:30pm - 4:45pm PDT Monday, June 23 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Maximizing Energy Efficiency in Spiking Neural Networks: A Dynamic Joint Pruning Framework
11:30am - 11:45am PDT Tuesday, June 24 3001, Level 3
AI
AI1: AI/ML Algorithms
Research Manuscript
MetaDSE: A Few-Shot Meta-Learning Framework for Cross-Workload CPU Design Space Exploration
2:30pm - 2:45pm PDT Wednesday, June 25 3001, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
MOSS: Multi-Modal Representation Learning on Sequential Circuits
11:00am - 11:15am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Networking
Work-in-Progress Poster
Ordering-Centric: A Scalable and Exact Method for Scheduling with Resource Constraints
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
2:15pm - 2:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Networking
Work-in-Progress Poster
Unary Positional System: Flexible Balance of Hardware Area and Performance
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby