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Organization

Cadence Design Systems, Inc.
Contributors
Neha Agrawal
Xin Ai
Narender Akilla
Narendra Akilla
Chuck Alpert
Pradeep Bagavathiappan
Gabriela Bahia
Anunay Bajaj
Dan Baldwin
Akshita Bansal
Joseph Bauer
Ben Beaumont
Fabien Campana
Ankur Chavhan
Daniel Cross
Yun Dai
Craig Deaton
Sravanthi Gajjala
Anindita Gangwar
Arnold Ginetti
Mariane Goncalves
Ketki Gosavi
Mohit Gupta
Hakan Hjort
Yu-Ling Hsu
Shao-Lun Huang
Sorna Inian
Sorna Inian
Prayes Jain
Vinesh Jayaraman
Gustavo Junquiera
Lakshmidas K
Atharva Kakde
Gang Kang
Gang Kang
Krunal Kapadiya
Vinod Kariat
Kushal Koolwal
Amit Kumar
Arvind Kumar
Ashish Kumar
Vishesh Kumar
Tulio Leao
Siang-Yun Lee
Mike Lin
Jian Liu
Jian Liu
Sainan Lu
Lars Lundgren
Chayan Majumder
Parv Malhotra
Hitesh Marwah
Loknath Moogi
Stephen Morais
Naresh Mummidivarapu
Clarice Oliveira
Gruheshkumar Patel
Nehal Patel
Amrita Patil
Bassilios Petrakis
Praveen Pillai
Riya Raj
Sakthivel Ramaiah
Kishan Ramesh
Sascha Richter
Heinz Riener
Laurent Saint-Marcel
Gowry Sankar
Erik Seligman
Stimit Shah
Gowry Shanmugam
Shyam Sharma
Shinyu Shiau
Anshul Singhal
Ankush Sood
Kirti Srivastava
Dharini Subashchandran
Kumar Subramani
Yingxin Sun
Yingxin Sun
Sai Asrith Tabdil
Yashodhara Tarey
Nirav Toliya
Junie Um
Gourav Uppal
Kaushal Vala
Xukang Wu
Xiaoyan Xiong
Xiaoyan Xiong
Albert Zeng
Jiyue Zhu
Jiyue Zhu
Session Chairs
Prabal Basu
Presentations
Engineering Poster
Networking
3D-IC Heterogeneous System Implementation using Virtuoso Studio and Integrity System Planner
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
3DIC Thermal-Aware Early Design Optimization
4:00pm - 4:15pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Networking
Work-in-Progress Poster
A Fast and Accurate Thermal Solver for Chip Thermal Throttling Analysis
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Poster
Networking
A Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECO
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Ancillary Meeting
Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?
12:00pm - 1:30pm PDT Tuesday, June 24 2006, Level 2
Engineering Poster
Networking
Activity-Based Power Density Optimization
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Advanced State Space Tunneling: Debug Your Formal Complexity Using Waveforms!
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
AI-enabled Efficient Extraction of Entire Advanced IC Package
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Poster
AI-ML meets SPICE to achieve 6-sigma Accuracy: A Revolution in Statistical Analysis
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
An advanced multi-vector optimization methodology to enhance power performance in scaled-down technology nodes.
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
An Efficient Methodology of Analyzing Rush Current in Power Gated Design
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Approach For Quality DV Using C2RTL For Algorithmic Designs Authors: Neema Agarwal, Himanshu Chauhan, Harsh Setia, Atharva Mahesh Kakde, Ketki Gosavi
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Research Panel
Beyond Limits: Packaging, Cryogenic, and New Cooling Strategies for Future Computing
10:30am - 12:00pm PDT Tuesday, June 24 3012, Level 3
Systems
Engineering Poster
Networking
Design Optimization of ASIC Designs via AI-driven RTL-to-GDS Optimization with Floorplanning
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Research Manuscript
Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation
3:30pm - 3:45pm PDT Wednesday, June 25 3004, Level 3
EDA
EDA2: Design Verification and Validation
Hands-On Training Session
Enabling Seamless Hybrid Cloud Transitions for EDA & Systems Design with Cadence True Hybrid Cloud
2:45pm - 5:45pm PDT Monday, June 23 2006, Level 2
Engineering Poster
Networking
Enhancing Timing Closure in High-Frequency Designs through Precise Latency Control and Timing-Aware Sink Assignment
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Ensuring DRAM Compliance: Novel Verification Techniques for Refresh and Refresh Management in Modern Dram Architecture
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Formal meets Simulation: Accelerate Verification closure using Multiplatform technologies
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Formal signoff for Cross-Module Design logic: A novel approach to manage formal scope in increasingly complex systems
2:15pm - 2:30pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Engineering Presentation
Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimization
3:45pm - 4:00pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Engineering Presentation
High Performance Extraction of 2.5D/3D-IC Package
4:45pm - 5:00pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Engineering Poster
IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Exhibitor Forum
Intelligent Extraction of Advanced IC Package
10:30am - 11:00am PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Research Manuscript
Logic Restructuring with Preserved Logic Blocks
4:15pm - 4:30pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Engineering Poster
Networking
Machine Learning accelerated distributed computing Place and Route framework for High Performance CPU designs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
Out of The Box Techniques for Data Path Verification
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Tutorial
Powering the Future: Mastering IEEE 2416 System Level Power Modeling Standard for Low-Power AI and Beyond
9:00am - 12:30pm PDT Sunday, June 22 3008, Level 3
AI
Sunday Program
Engineering Poster
Networking
Reducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE Technology
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Securing Chiplet Integration: A System-in-Package Security Architecture.
3:30pm - 3:45pm PDT Monday, June 23 2008, Level 2
AI
Systems and Software
Chiplet
Engineering Poster
Networking
Solving Configuration Challenge with SVRAND Verification Flow
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Statistical analysis using AI-ML enabled SPICE solution to get tail samples for high linearity delta sigma converters
11:30am - 11:45am PDT Monday, June 23 2010, Level 2
AI
IP
Exhibitor Forum
The Renaissance of EDA Startups
2:30pm - 3:15pm PDT Tuesday, June 24 Exhibitor Forum, Level 1 Exhibit Hall
Engineering Poster
Networking
timing-aware smart PG fill
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
USB4 MAC Verification: Overcoming Serial Interface and Simulation Time Challenges
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Sessions
Research Manuscript
Watts Up? AI/ML Enabled Advances in Power and Thermal Integrity
3:30pm - 5:30pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization