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Organization

Southeast University
Contributors
Tao Bai
Hao Cai
Peng Cao
Yichao Cao
Pengju Chen
Shikuang Chen
Zeyuan Deng
Fang Dong
Yichao Dong
Haoran Du
Yushu Du
Hao Gu
Zhenghui Guo
Xiaomeng Han
Mingwei He
Xiangfei Hu
Yuchen Hu
Zhe Jiang
Junming Jiao
Xinyao Jiao
Kai Jing
Borui Li
Yiming Li
Bo Liu
Yuchen Liu
Zhichao Liu
Junyang Lu
Dan Niu
Keyu Peng
Lizheng Ren
Weiwei Shan
Dian Shen
Longxing Shi
Xin Si
Fan Sun
Jialin Sun
Zhihang Tan
Chao Wang
Chao Wang
Hui Wang
Jing Wang
Shuai Wang
Shuai Wang
Tinglue Wang
Xi Wang
Xiaoxuan Wang
Xing Wang
Youwen Wang
Yinuo Wu
Tiange Xia
Depeng Xie
Ke Xu
Ning Xu
Hao Yan
Jun Yang
Junhao Ye
Dean You
Chen Zhang
Dekang Zhang
Shiyue Zhang
Xinglin Zheng
Zhengzhe Zheng
Haochang Zhi
Jie Zhou
Binwu Zhu
Ziran Zhu
Zihan Zou
Presentations
Research Manuscript
A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
11:30am - 11:45am PDT Monday, June 23 3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Networking
Work-in-Progress Poster
Accelerating IC Thermal Simulation Data Generation via Block Krylov and Operator Action
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
4:45pm - 5:00pm PDT Monday, June 23 3008, Level 3
Systems
SYS2: Design of Cyber-Physical Systems and IoT
Research Manuscript
BBAL: A Bidirectional Block Floating Point-Based Quantization Accelerator for Large Language Models
5:00pm - 5:15pm PDT Tuesday, June 24 3000, Level 3
AI
AI3: AI/ML Architecture Design
Research Manuscript
Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells
11:30am - 11:45am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization
10:45am - 11:00am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
3:45pm - 4:00pm PDT Wednesday, June 25 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
4:30pm - 4:45pm PDT Wednesday, June 25 3008, Level 3
Systems
SYS6: Time-Critical and Fault-Tolerant System Design
Research Manuscript
G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
11:15am - 11:30am PDT Monday, June 23 3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Research Manuscript
HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
4:00pm - 4:15pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
InfScaler: Enabling Efficient ML Inference Serving on Multi-Accelerator Edge Devices via Asymmetric Auto-Scaling
3:45pm - 4:00pm PDT Monday, June 23 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
4:15pm - 4:30pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA2: Design Verification and Validation
Late Breaking Results
Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Late Breaking Results
Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
5:15pm - 5:30pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS3: Embedded Software
Research Manuscript
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
4:00pm - 4:15pm PDT Monday, June 23 3008, Level 3
Systems
SYS2: Design of Cyber-Physical Systems and IoT
Research Manuscript
NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
5:00pm - 5:15pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Research Manuscript
NVR: Vector Runahead on NPUs for Sparse Memory Access
2:15pm - 2:30pm PDT Monday, June 23 3008, Level 3
Systems
SYS5: Embedded Memory and Storage Systems
Research Manuscript
OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation
4:45pm - 5:00pm PDT Wednesday, June 25 3001, Level 3
Design
DES2B: In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification
1:30pm - 1:45pm PDT Wednesday, June 25 3003, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Research Manuscript
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
5:00pm - 5:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
11:00am - 11:15am PDT Wednesday, June 25 3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Networking
Work-in-Progress Poster
Scalar Runahead
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
11:30am - 11:45am PDT Wednesday, June 25 3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
11:15am - 11:30am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Research Manuscript
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
4:15pm - 4:30pm PDT Tuesday, June 24 3008, Level 3
Systems
SYS3: Embedded Software
Research Manuscript
UVLLM: An Automated Universal RTL Verification Framework using LLMs
4:30pm - 4:45pm PDT Wednesday, June 25 3006, Level 3
Systems
SYS4: Embedded System Design Tools and Methodologies