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Organization

STMicroelectronics
Contributors
Fady Abouzeid
Davinder AGGARWAL
Stefano Angeli
Frederic Avellaneda
Ankur Bal
Michele Battista
Olivier Bayet
Savino Bellopede
Atul Bhargava
Chiara Bielli
Mario Blangiforti
Edoardo Bollea
Jean-Christophe Brignone
Marco Castellano
Simone Colle
Manvi Dhawan
Anil Dwivedi
Davide Fiorese
jean francois
Rajnish GARG
Vaibhav Garg
Ugo Garozzo
Ankit Gupta
ANUJ GUPTA
bipul halder
Abhishek Jain
Anupam Jain
Nitin Jain
Sanyam Jain
Nishant Kaundal
Lyubomir Kerachev
Amerjeet Kumar
Anil Kumar
Rahul Kumar
Aradhana Kumari
Suprbha Kumari
Paolo Mazzetti
Anand Mishra
Rajesh Narwal
Serge Nicoleau
Agata Notario
Biswarup Pal
Govind Pal
Michele Palma
Rahul pandey
Enrico Papa
Luca Francesco Perroni
Giuseppa Maria Pino
Luca Pulvirenti
Manmohan Rana
Anuradha Ray
Gianluca Rigano
Philippe Roche
Pravesh Saini
Davide Sanalitro
Neha Saxena
Ashutosh Singh
Krish Singh
Rajeev Singh
SHARMISTHA SINHA
Harshil UPADHYAY
aditya vasisth
David Vincenzoni
Anil Yadav
Anil yadav
Presentations
Engineering Presentation
A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment
2:30pm - 2:45pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Accelerating analog connectivity verification with Jasper: comparing formal methods to mixed simulation
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Advanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop Analysis
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
SKYTalk
AI Booster for R&D, Edge Computing, Chiplets, and Sustainability
1:00pm - 1:45pm PDT Wednesday, June 25 DAC Pavilion, Level 2 Exhibit Hall
Engineering Poster
AI-ML meets SPICE to achieve 6-sigma Accuracy: A Revolution in Statistical Analysis
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Boosting Low Power Verification Methodology: Introducing Power-Aware Formal Property Verification into the Flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Special Session
CDC-RDC Inter-operable Collateral Standardization
10:30am - 12:00pm PDT Monday, June 23 2008, Level 2
Back-End Design
Engineering Poster
Networking
Circuit Design and Optimization Methodology ensuring Area optimized, Robust and Reliable I/O Interface for Wide Range of Application use
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Design for Time Interleaving of Data using Sub-sampling Clocks
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Detection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS)
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
Early Mismatch Detection in Analog Layout Using PLS Netlist
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Presentation
Energy Efficient I3C IP Subsystem for Low Power IoT
11:00am - 11:15am PDT Wednesday, June 25 2010, Level 2
IP
Engineering Poster
Networking
Enhancing Design Quality through a High-Level Synthesis Flow in Neural Network-Based Keyword Spotting Systems
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Enhancing verification throughput in random tests regression with a novel machine learning engine
3:30pm - 3:45pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Poster
Networking
ESD EDA Verification Flow Applied to Smart Power IC's
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
High Figure of Merit Polyphase Decimation Core IP
11:30am - 11:45am PDT Wednesday, June 25 2010, Level 2
IP
Engineering Poster
Networking
Improving Digital Design performance and area using DSO.ai
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
IR-Aware Timing Analysis using Accurate DvD-PWL Flow for Advanced Technology Nodes
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Mitigating Routing Congestion in Automotive SoCs with ML based Power Grid Optimization
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers
4:15pm - 4:30pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Engineering Poster
Novel Shift-Left Methodology for System Power Integrity Analysis with Early Chip Power Model
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
2:00pm - 2:15pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
Networking
Reducing High di/dt Simultaneous Switching Noise in Advanced Multiprocessor SoCs
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Reducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE Technology
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards
4:42pm - 5:00pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Poster
Networking
Silicon Lifecycle Management in Automotive Design
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Statistical analysis using AI-ML enabled SPICE solution to get tail samples for high linearity delta sigma converters
11:30am - 11:45am PDT Monday, June 23 2010, Level 2
AI
IP
Networking
Work-in-Progress Poster
TEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric Prediction
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Engineering Poster
Networking
timing-aware smart PG fill
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Unlocking the power of AI-based verification apps for an innovative and efficient digital verification flow
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall