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Organization

Beijing University of Posts and Telecommunications
Contributors
Guande Dong
Donghao Guo
Feng Guo
Li Guo
Yuanchun Guo
Renjing Hou
Jingyu Jia
Shigang Li
Bingyan Liu
Jiawei Liu
Xinya Luan
Yi Man
Xingyu Qin
yulong sha
Chuan Shi
Kai Shi
Zheng Weng
Yueyue Xi
zhensheng xian
Shibiao Xu
Wenhao Xu
Jianwang Zhai
Zherui Zhang
Kang Zhao
Jie Zhou
Presentations
Research Manuscript
CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
11:45am - 12:00pm PDT Tuesday, June 24 3006, Level 3
Security
SEC1: AI/ML Security/Privacy
Research Manuscript
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
3:30pm - 3:45pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
Networking
Work-in-Progress Poster
HLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian Optimization
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
3:45pm - 4:00pm PDT Monday, June 23 3006, Level 3
EDA
EDA4: Power Analysis and Optimization
Research Manuscript
ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
11:00am - 11:15am PDT Monday, June 23 3000, Level 3
AI
AI1: AI/ML Algorithms
Networking
Work-in-Progress Poster
ParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement Learning
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
PracMHBench: Re-evaluating Model-Heterogeneous Federated Learning Based on Practical Edge Device Constraints
10:30am - 10:45am PDT Wednesday, June 25 3001, Level 3
AI
AI4: AI/ML System and Platform Design
Networking
Work-in-Progress Poster
Rethinking Translation Robustness for Reliable Convolutional Segmentation Architecture
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Networking
Work-in-Progress Poster
Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
Truly Pre-Routing Timing Prediction via Considering Power Delivery Networks
11:15am - 11:30am PDT Monday, June 23 3004, Level 3
EDA
EDA3: Timing Analysis and Optimization
Networking
Work-in-Progress Poster
Unary Positional System: Flexible Balance of Hardware Area and Performance
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
Research Manuscript
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
3:45pm - 4:00pm PDT Tuesday, June 24 3002, Level 3
Design
DES1: SoC, Heterogeneous, and Reconfigurable Architectures