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Organization

Texas Instruments
Contributors
Subhadeep Aich
Aswin B
Lakshmanan Balasubramanian
Rakesh Bansal
Ayushi Bapna
Abhranil Bose
Piyushkumar Chaniyara
Avinash Chaudhary
Anurag Choudhury
Stefan Dannenberger
Mangesh Dhantole
Vishal Diwan
Pervez Garg
Subhadeep Ghosh
Roger Griesmer
Robin Hoel
Faeq Hussain
Ayush Jodh
Sagar Jogur
Vivek Joshi
Torjus Kallerud
Ninad Khire
Atul Lele
Gayathri M
Pooja Madhusoodhanan
Harish Maruthiyodan
Harish Maruthiyodhan
Megha Mendu
Ashutosh Mishra
Prachi Mishra
Arif Mohammed
Aniruddha N
Keerthi Nori
Ashwini Padoor
Abhinav Parashar
Rubin Parekhji
Jahnavi Pragada
Krishan Prajapat
Kavithaa Rajagopalan
Kavithaa rajagopalan
Parthasarathy Ramesh
Satish Sajjanar
Rajanikant Sakariya
Suraj Salian
Tejas Salunkhe
Sooraj Sekhar
Bhavya Shah
Yogeshwaran Shanmugam
Aadhar Sharma
Mohit Shrivastava
Arshdeep Singh
Kumar Singh
Rishabh Singh
UTKARSHA SUMAN
Murtaza Tankiwala
Ben Thomas
Mohan Udayakumar
Abhishek Verma
Sukhmani Virk
Prasanth Viswanathan Pillai
Rakesh YC
Yash Zavar
Presentations
Engineering Presentation
A Completely Digital, Low-Power, and Low-Area Phase Synchronization Architecture for Meso-Synchronous Clock Domains Supporting Dynamic Frequency Scaling
1:45pm - 2:00pm PDT Monday, June 23 2010, Level 2
AI
IP
Chiplet
Engineering Poster
Networking
A constructive approach to Left-shift preliminary identification of critical silicon breaking anomalies
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
A Novel Feedthrough Insertion Methodology for Hierarchical SOC Designs: Achieving Reduction in Die Area
1:30pm - 1:45pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Poster
Networking
A Novel Test Point Insertion Methodology for Enhanced Test Efficiency and Improved Design Quality
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
AACT: Automated Analog Coverage Tool for Mixed Signal Verification
10:45am - 11:00am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Poster
Networking
Accelerating IR Simulation Workflows with Automated Setup and Results Data Visualization Tools for Digital Designs using Voltus Platform
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
AI/ML Driven Optimization for Efficient ATPG in Large Scale Designs
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
AUTOLNKGEN: Automated Random Linker File Generation Framework for Heterogenous SoC Verification & Validation
11:00am - 11:15am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Poster
Networking
Automated generation of ISO 21434 Verification Work Products
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated modelling and assertion generator for verifying any generic complex IO Controllers
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automation of Shmoo Engine based Pre-Si BDI Testing
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Comprehensive Interconnect Verification – Leveraging Formal Methodology & Automation for verifying Address Decoding and Arbiter Verification, Performance Analysis
2:45pm - 3:00pm PDT Tuesday, June 24 2010, Level 2
Front-End Design
Engineering Poster
Networking
Contemporary PPAS Optimization Strategies in Physical Implementation of Digital SoCs – A Case Study
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Design Quality Improvement Through Automation
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Dynamic Optimization of Skew Balancing through an Innovative Correct-by-Construct Path Delay Query Technique
2:45pm - 3:00pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Poster
ENZO: Comprehensive DFT Methodology for MCU class of devices
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Expediting custom core SOC verification and coverage driven firmware sign-off using ESWD & Verisium Debug
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Hybrid and Adaptive Digital Filter architecture for Robust tracking of On-chip Low Frequency Oscillator Period, enabling Crystal less BLE operation in Low Power Wireless MCUs
11:15am - 11:30am PDT Wednesday, June 25 2010, Level 2
IP
Research Manuscript
Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
1:45pm - 2:00pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA9: Design for Test and Silicon Lifecycle Management
Engineering Poster
Networking
Revolutionising SOC Verification through System Verilog EEnet-Enhanced Behavioural Model for Precision in Analog IP Characterisation
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Streamlined RTL Clock Management: A Python Framework for Clock Tracing, Clock Spec Verification and STA Constraint Generation
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall