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Organization

Samsung
Contributors
Neema Agarwal
MooKyu Bae
Youngjae Bae
Sungsu Byun
Silwan Chang
xun chen
Narasimha Chinni
Dayeon Cho
JiHo Cho
Kyoungsun Cho
Sangyeun Cho
Jungyun Choi
Deepayan Dasgupta
Vijaya Gupta
Seungik Ha
Sangwoo Han
Jaein Hong
Seokha Hong
Seungkwang Hong
SungHoi Hur
Bosun Hwang
Eunju Hwang
Hyunchul Hwang
Jinyoung Hwang
JungSeok Hwang
Jaewoo Im
Silwan Jang
jaeyeong jeon
Junha Jeon
Woojin Jin
Kyeongrok Jo
Kun Joo
Moonki Jun
Kibeen Jung
Minho Jung
ByeongKeun Kang
Donghyub Kang
Gwonhyuk Kang
HyunSeo Kang
Kunhyuk Kang
Kyungsu Kang
Kyungsu Kang
Sunggu Kang
Sunil Kashide
Byeonghui Kim
Byungsu Kim
Dongwhee Kim
Haeun Kim
Hyundon Kim
Hyung-Ock Kim
Jeongyeol Kim
Jinbeom Kim
Jinwon Kim
Jisoo Kim
Jongbeom Kim
jungho kim
Ki-Ok Kim
Min-su Kim
Myeongjin Kim
Namyoung Kim
Sichan Kim
WanDong Kim
Wook Kim
Yong geol Kim
YoonJung Kim
Youngwook Kim
Gopikrishna Kommidi
HyuckJoon Kwon
Bonghyun Lee
Byunghoon Lee
Daeseong Lee
DongYoung Lee
DooYoung Lee
Hankyu Lee
Hyoungwook Lee
Jaeha Lee
Jeongyoon Lee
Jongyoul Lee
Joowan Lee
Juhwan Lee
Mintae Lee
Sangwon Lee
Seunghwan Lee
Seungsoo Lee
taeyoon Lee
Yongjeong Lee
Suk Hwan Lim
Sangkwon Moon
Kibum Nam
Changyong Oh
Hyun-kyo Oh
JungSeok Oh
Yoonjoong Oh
Youngmin Oh
Yujin Oh
MinKwon On
Hyunman Park
Jaesung Park
Jongseong Park
Sanghune Park
Sangun Park
Taewon Park
Kangho Roh
Seongho Roh
pradeep sahoo
Tanuj Sengupta
Sungyoul Seo
Youngho Seo
Shekhar Sharma
Prem Sinha
Jaeyoung So
Youngsoo Sohn
Ki-Whan Song
Garima Srivastava
Sean Sun
Jooho Wang
Donghwi Won
Kevin Yee
Haemin Yoo
TaeYang YOU
Presentations
Engineering Poster
Networking
A New Virtual IP Modeling Methodology for Re-usability in Heterogeneous Virtual Platforms
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
A Novel approach for workload based GPU datapath power optimization
11:30am - 11:45am PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Engineering Poster
A Novel Solution for Parasitic resistance analysis: Calibre PERC-Driven Optimization for PEX Quality Assurance
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Accelerated SoC Level Android Home Screen Bring-up, System Software Development and Validation at Pre-Silicon with Advanced Hybrid Emulation Methodology
3:30pm - 3:48pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Research Manuscript
Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation
11:45am - 12:00pm PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Engineering Presentation
An Automated and Scalable Monitor-and-Checker solution for SMMU verification in Multi-Die SoCs
4:30pm - 4:45pm PDT Tuesday, June 24 2010, Level 2
AI
Front-End Design
Chiplet
Engineering Presentation
An engineering approach to high performance scannable flip flops embedding functional logics
4:15pm - 4:30pm PDT Monday, June 23 2010, Level 2
IP
Engineering Poster
Approach For Quality DV Using C2RTL For Algorithmic Designs Authors: Neema Agarwal, Himanshu Chauhan, Harsh Setia, Atharva Mahesh Kakde, Ketki Gosavi
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Automated "Spec to Sign-Off" of CSR and Integration Verification at SOC
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Networking
Work-in-Progress Poster
Black-box Auto-Tuning for Customized SSD Firmware Parameters under Constraints
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Panel
Chips and Systems for AI: Gains, Drains and the Uncharted Road Ahead
10:30am - 12:00pm PDT Wednesday, June 25 3012, Level 3
AI
Engineering Poster
Networking
Clock H-tree exploration in BSPDN
12:15pm - 1:15pm PDT Wednesday, June 25 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
Networking
Comprehensive solution for Optimizing and Accelerating Gate level simulation for complex SOCs
5:00pm - 6:00pm PDT Monday, June 23 Engineering Posters, Level 2 Exhibit Hall
Engineering Poster
CTS with Machine Learning NDR
5:00pm - 6:00pm PDT Tuesday, June 24 Engineering Posters, Level 2 Exhibit Hall
Engineering Presentation
Efficient Hardware Fuzzing based on SystemC
11:15am - 11:30am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Engineering Special Session
Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration
1:30pm - 3:00pm PDT Monday, June 23 2008, Level 2
AI
Back-End Design
Chiplet
Engineering Presentation
Enhanced Power Saving with System-on-Chip and Software Design Optimization
3:48pm - 4:06pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Presentation
Generation of Failure Inspection Pattern without Design Impact during P&R in BSPDN Design
11:30am - 11:45am PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Presentation
Improving Functional Accuracy of Virtual Platform Based on Coreless Test Framework in Early Development Stage
4:06pm - 4:24pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Research Manuscript
INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive Transformers
11:00am - 11:15am PDT Monday, June 23 3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test
Engineering Presentation
IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Interposer with 3D-IC Platform
1:30pm - 1:45pm PDT Monday, June 23 2012, Level 2
AI
Back-End Design
Chiplet
Late Breaking Results
Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Engineering Special Session
LLM Innovations: Mirage or Milestone ?
1:30pm - 3:00pm PDT Tuesday, June 24 2008, Level 2
AI
Systems and Software
Engineering Presentation
ML based PPA Push using XAI
1:45pm - 2:00pm PDT Tuesday, June 24 2012, Level 2
AI
Back-End Design
Engineering Presentation
Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification
11:30am - 11:45am PDT Wednesday, June 25 2008, Level 2
Front-End Design
Networking
Work-in-Progress Poster
Opt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell Design
6:00pm - 7:00pm PDT Monday, June 23 Level 2 Lobby
Research Manuscript
PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators
3:45pm - 4:00pm PDT Tuesday, June 24 3003, Level 3
Design
DES4: Digital and Analog Circuits
Tutorial
Powering the Future: Mastering IEEE 2416 System Level Power Modeling Standard for Low-Power AI and Beyond
9:00am - 12:30pm PDT Sunday, June 22 3008, Level 3
AI
Sunday Program
Engineering Presentation
Scenario-based Mixed Signal Layout Generator using Generation APIs for Memory
3:30pm - 3:45pm PDT Monday, June 23 2010, Level 2
IP
Engineering Presentation
Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework
10:30am - 10:45am PDT Tuesday, June 24 2010, Level 2
Front-End Design
Chiplet
Engineering Presentation
Thermal Characteristic Analysis of Back-Side Power Delivery Network
3:45pm - 4:00pm PDT Tuesday, June 24 2012, Level 2
Back-End Design
Chiplet
Research Manuscript
zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
10:45am - 11:00am PDT Wednesday, June 25 3002, Level 3
Security
SEC1: AI/ML Security/Privacy