Presentation
Static Sign-Off Methodologies: Liberating Functional Verification from Boolean Shackles
DescriptionEngineering teams are increasingly prioritizing early functional verification, achieving targeted verification and sign-off across more domains during RTL design—well before simulation. This early sign-off approach dramatically reduces downstream engineering changes and iterations.
Successfully deploying sign-off during RTL design requires both tool speed and the scalability to handle IPs and SoCs, along with complete coverage that detects all targeted errors.
Because static sign-off leverages abstract checking methods rather than the Boolean analysis used by simulation and formal verification, it delivers 10–100X faster runtimes, multi-billion-gate capacity, and a more efficient setup process. Additionally, its support for user-defined rules enables in-depth analysis for emerging applications where design requirements continue to evolve.
Multiple experts will share production-proven methodology advances and best practices across key static sign-off applications, including: 1) RTL linting, 2) clock domain crossing, 3) reset domain crossing, 4) design-for-testability, 5) connectivity and glitch detection, and 6) hardware security sign-off.
Attendees will gain a deeper understanding of static sign-off methodologies, along with practical insights tailored to specific applications.
Successfully deploying sign-off during RTL design requires both tool speed and the scalability to handle IPs and SoCs, along with complete coverage that detects all targeted errors.
Because static sign-off leverages abstract checking methods rather than the Boolean analysis used by simulation and formal verification, it delivers 10–100X faster runtimes, multi-billion-gate capacity, and a more efficient setup process. Additionally, its support for user-defined rules enables in-depth analysis for emerging applications where design requirements continue to evolve.
Multiple experts will share production-proven methodology advances and best practices across key static sign-off applications, including: 1) RTL linting, 2) clock domain crossing, 3) reset domain crossing, 4) design-for-testability, 5) connectivity and glitch detection, and 6) hardware security sign-off.
Attendees will gain a deeper understanding of static sign-off methodologies, along with practical insights tailored to specific applications.
Event Type
Exhibitor Forum
TimeMonday, June 231:45pm - 2:15pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall