Presentation
GenAI-Powered Cyber-Resilient RTL for Secure and Robust Semiconductor Devices
DescriptionSemiconductor devices face increasing risks of attacks, exploits, and cyber vulnerabilities. Complex supply chains, distribution channels, and in-field deployments make it difficult to secure a device at every point in its lifespan. This session will focus on a new technique that hardens semiconductor designs to thwart malicious actors from embedding Trojans, introducing design flaws, or implementing manufacturing changes that compromise device functionality, reliability, or data integrity.
We will share a patented design hardening approach that not only supports thorough validation but also enables quantitative assessment of security improvements at RTL level. Central to this approach is intelligent instrumentation, based on a sophisticated method that precisely identifies and characterizes chip vulnerabilities, assesses their severity and impact, and strategically implements countermeasures. Our method leverages supervised machine learning to make data-driven tradeoff between security efficacy and cost ensuring optimal design instrumentation.
Attendees will gain insight into advanced GenAI and ML-based design for security and trust methodology that takes a proactive approach to microelectronics security at the RTL level. The session will detail how semiconductor devices can be made secure - monitored for anomalous behavior - from design to fabrication to deployment.
We will share a patented design hardening approach that not only supports thorough validation but also enables quantitative assessment of security improvements at RTL level. Central to this approach is intelligent instrumentation, based on a sophisticated method that precisely identifies and characterizes chip vulnerabilities, assesses their severity and impact, and strategically implements countermeasures. Our method leverages supervised machine learning to make data-driven tradeoff between security efficacy and cost ensuring optimal design instrumentation.
Attendees will gain insight into advanced GenAI and ML-based design for security and trust methodology that takes a proactive approach to microelectronics security at the RTL level. The session will detail how semiconductor devices can be made secure - monitored for anomalous behavior - from design to fabrication to deployment.
Event Type
Exhibitor Forum
TimeWednesday, June 2510:30am - 11:00am PDT
LocationExhibitor Forum, Level 1 Exhibit Hall