Presentation
CoverAgent: How Agentic AI is Redefining Functional Coverage Closure
DescriptionFunctional coverage closure remains one of the most persistent and resource-intensive challenges in RTL verification. Despite decades of EDA tool evolution, coverage gaps often require manual analysis, ad hoc scripting, and repeated testbench iterations. In this talk, we introduce CoverAgent, an agentic AI system purpose-built to identify, target, and close the last functional coverage gaps that conventional tools and workflows leave behind.
CoverAgent operates as an autonomous agent within your existing verification environment. It analyzes coverage reports, understands testbench structure, infers unreachable states, and autonomously proposes targeted stimuli and constraint adjustments — all without rewriting your entire environment. Built on a foundation of LLMs and agent-based reasoning, CoverAgent bridges the usability gap between design intent and simulation behavior.
We present real-world case studies demonstrating how CoverAgent accelerated closure by 80% in complex SoC environments, uncovered unreachable bins missed by traditional tools, and improved the productivity of design verification engineers without sacrificing control or interpretability.
Whether you're building CPUs, accelerators, or memory subsystems, CoverAgent fits seamlessly into your UVM or SystemVerilog flow. It complements existing commercial tools, providing a new dimension of intelligence to the verification loop.
Join us to see how agentic AI can supercharge your coverage strategy, reduce manual effort, and make coverage closure not just achievable — but efficient, scalable, and even enjoyable.
CoverAgent operates as an autonomous agent within your existing verification environment. It analyzes coverage reports, understands testbench structure, infers unreachable states, and autonomously proposes targeted stimuli and constraint adjustments — all without rewriting your entire environment. Built on a foundation of LLMs and agent-based reasoning, CoverAgent bridges the usability gap between design intent and simulation behavior.
We present real-world case studies demonstrating how CoverAgent accelerated closure by 80% in complex SoC environments, uncovered unreachable bins missed by traditional tools, and improved the productivity of design verification engineers without sacrificing control or interpretability.
Whether you're building CPUs, accelerators, or memory subsystems, CoverAgent fits seamlessly into your UVM or SystemVerilog flow. It complements existing commercial tools, providing a new dimension of intelligence to the verification loop.
Join us to see how agentic AI can supercharge your coverage strategy, reduce manual effort, and make coverage closure not just achievable — but efficient, scalable, and even enjoyable.
Event Type
Exhibitor Forum
TimeTuesday, June 241:45pm - 2:15pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall