Presentation
Beyond Breaking the Bottleneck: Smart Verification for Modern Complexity
DescriptionVerification is increasingly becoming the defining constraint in semiconductor design, as complexity surges across software-defined architectures, massive 3D IC and chiplet-based designs, and exploding security and safety-critical requirements. Traditional approaches—relying on large regression suites, manual coverage analysis, and isolated debug—are struggling to keep up. This session explores how scalable, intelligent verification strategies are addressing these challenges through connected workflows, AI-enhanced automation, and data-driven insights. We’ll discuss how to shift from reactive debugging to proactive verification planning, and how to improve engineering throughput without scaling teams or compute linearly. Real-world examples will illustrate how teams are reducing debug effort, accelerating coverage closure, and unlocking new levels of productivity. Attendees will leave with practical ideas for building smarter verification flows that are engineered for modern complexity—not just more speed, but better focus resulting in improved productivity.
Presenter
Vice President & General Manager, Design Verification Technologies
Event Type
Exhibitor Forum
TimeMonday, June 2312:00pm - 12:30pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall