Presentation
SLM Is the New DFT – Are You Ready?
DescriptionIt's Monday morning, and you get pulled into an ad-hoc meeting to discuss your latest SoC's performance and power targets. The chip is missing performance targets by 15%, and now your team needs to raise the power budget to meet the spec. The entire process devolves into a flurry of finger-pointing without concrete evidence of what went wrong. When it comes to your $200M SoC project, is it better to guess or know what went wrong?
Most modern SoCs mitigate the guesswork by leveraging DFT (Design for Test) techniques, like adding more memory BIST or improving functional coverage. However, these tests were meant for verifying connectivity and basic functionality. What happens when you need the next level of observability and analytics to improve power, performance, yield, and reliability? These next-level analytics are driving the adoption of silicon lifecycle management (SLM) platforms.
For those unfamiliar, SLM platforms combine a variety of specialized on-die sensors with an analytics engine to improve power margins, manufacturing yield, silicon longevity, failure analysis, and enable predictive maintenance. The targeted analytics enable design optimizations at each stage of the design lifecycle, including pre-silicon through in-field operations.
As SoCs grow in size, complexity, and cost, expanding visibility is important. SLM is not yet broadly adopted in the industry, but just like DFT went from a concept to a norm SLM is expected to follow the same path.
Our discussion will briefly explore the current state of silicon testing and its evolution from bench characterization and ATE to in-field testing. It will also delve into different silicon lifecycle solutions and how they fit in each design phase. Together, we will answer some of the following questions from an IP, analytics platform, and testing perspective:
• How is testing done today?
• What are the limitations, and how can they be overcome?
• If the new test capabilities include the ability to test in the field, what benefits does that bring/how can that capability be leveraged?
• What is required to enable this capability, and how does it affect system architecture?
• How does this impact test at the ATE, chiplet, SLT, and in-field stages?
• What is the adoption path for this technology
Most modern SoCs mitigate the guesswork by leveraging DFT (Design for Test) techniques, like adding more memory BIST or improving functional coverage. However, these tests were meant for verifying connectivity and basic functionality. What happens when you need the next level of observability and analytics to improve power, performance, yield, and reliability? These next-level analytics are driving the adoption of silicon lifecycle management (SLM) platforms.
For those unfamiliar, SLM platforms combine a variety of specialized on-die sensors with an analytics engine to improve power margins, manufacturing yield, silicon longevity, failure analysis, and enable predictive maintenance. The targeted analytics enable design optimizations at each stage of the design lifecycle, including pre-silicon through in-field operations.
As SoCs grow in size, complexity, and cost, expanding visibility is important. SLM is not yet broadly adopted in the industry, but just like DFT went from a concept to a norm SLM is expected to follow the same path.
Our discussion will briefly explore the current state of silicon testing and its evolution from bench characterization and ATE to in-field testing. It will also delve into different silicon lifecycle solutions and how they fit in each design phase. Together, we will answer some of the following questions from an IP, analytics platform, and testing perspective:
• How is testing done today?
• What are the limitations, and how can they be overcome?
• If the new test capabilities include the ability to test in the field, what benefits does that bring/how can that capability be leveraged?
• What is required to enable this capability, and how does it affect system architecture?
• How does this impact test at the ATE, chiplet, SLT, and in-field stages?
• What is the adoption path for this technology
Organizer
Event Type
Engineering Special Session
TimeMonday, June 233:30pm - 5:00pm PDT
Location2012, Level 2
Back-End Design