Presentation
ESD EDA Verification Flow Applied to Smart Power IC's
DescriptionThe ESD validation flow integrates multiple verification steps to ensure robustness in IC design, with a significant advancement brought by the EARLY VDROP tool. Unlike conventional methods that assess ESD compliance post-layout, EARLY VDROP operates at the schematic level, allowing early detection of possible ESD network problems at the schematic level. This proactive approach enables to detect and address potential voltage drop issues early, which can significantly reduce downstream failures.
The flow, built upon Siemens EDA's Calibre tool suite, consists of three main stages: Schematic-Level Topology Checks, which validate the ESD network architecture across various hierarchical levels (from cell to domain to top level); Layout-Level Current Density Checks, which examine current density in the IC layout to confirm compliance with ESD standards; and finally, Schematic-Level Voltage Drop Checks, identifying weakness paths inside protected circuitry that cannot sustain the voltage drop generated by the ESD protection network during an ESD event.
Together, these steps form a comprehensive ESD validation workflow, with EARLY VDROP enabling early-stage, schematic-based risk assessment. Preliminary results show a strong correlation with traditional methods, reinforcing its effectiveness and value in streamlining ESD compliance.
The flow, built upon Siemens EDA's Calibre tool suite, consists of three main stages: Schematic-Level Topology Checks, which validate the ESD network architecture across various hierarchical levels (from cell to domain to top level); Layout-Level Current Density Checks, which examine current density in the IC layout to confirm compliance with ESD standards; and finally, Schematic-Level Voltage Drop Checks, identifying weakness paths inside protected circuitry that cannot sustain the voltage drop generated by the ESD protection network during an ESD event.
Together, these steps form a comprehensive ESD validation workflow, with EARLY VDROP enabling early-stage, schematic-based risk assessment. Preliminary results show a strong correlation with traditional methods, reinforcing its effectiveness and value in streamlining ESD compliance.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall