Presentation
A new methodology to generate a multitude of SoC configurations quickly
DescriptionWithin Arm a new unit has been built to provide SoC solutions to their customers. One of the biggest problems we faced when designing SoCs was need to rearrange the hierarchy to match physical implementation needs. As the targeted applications are highly complex, changing the hierarchy manually or using traditional methodologies was not affordable.
We have developed a new flow based on Defacto's SoC Compiler to be able to generate multiple configurations within one day. The presented flow enables to generate a new SoC hierarchy of one of extremely large Arm-based SoC design in just one hour rather than more than 24hours with the original way.
This flow enables to drastically reduce the overall TAT to generate new RTL which leads to have much more RTL configurations to explore and compare towards better PPA.
We have developed a new flow based on Defacto's SoC Compiler to be able to generate multiple configurations within one day. The presented flow enables to generate a new SoC hierarchy of one of extremely large Arm-based SoC design in just one hour rather than more than 24hours with the original way.
This flow enables to drastically reduce the overall TAT to generate new RTL which leads to have much more RTL configurations to explore and compare towards better PPA.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall