Presentation
Simulation-Aware Gate Resistance Modeling before Post-Layout Simulation
DescriptionA novel simulation-aware MOS gate resistance modeling is developed in this work which advances the state-of-the-art RC extraction in layout dependence of gate resistance and has several major contributions. First, gate resistance topology and corresponding solutions in both layout scenarios of contact on field poly and on gate poly are explored. In addition, an efficient and accurate gate resistance diamond-shape network is proposed specifically for layout style of contact on gate poly. Second, the difference of effective gate resistance between extraction and simulation conditions are illustrated and the corresponding performance and layout optimization for gate resistance is shown. Third, from the perspective of circuit performance, the comparison of gate resistance between native network provided by commercial RC extraction tools and diamond-shape network are discussed.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall