Presentation
1.1% Die area reduction in Consumer and Industrial MCU-Production SoC meeting Analog Routing and performance Targets
DescriptionThe quest for miniaturization in chip design for Consumer and Industrial SOC applications like low end MCU, is fraught with challenges that can inflate die size and compromise PPA target and efficiency aligned to product specification.On entry level general purpose MCU SoC any die size reduction has huge potential to save dollars on each device and earn profit.
Improvement in Padring design, IO channel estimates, CR overheads and Power Delivery Network (PDN) design which resulted in better Floorplan efficiency.Clock tree development addressed cell density hot spots and skew reduction. Addressed early routability of design in reduced die area including lesser net detours.Addressed early IR/EM, Custom Route and DRC-Max density signoff checks. Addressed various techniques in STA to reduce Timing ECO cycles to achieve schedule
Technical challenges faced during Floorplan and Clock tree optimizations which led to timely Tapeout with better-than-expected quality of results.Some of the methods and Techniques were re used in projects of similar complexities and size.
Improvement in Padring design, IO channel estimates, CR overheads and Power Delivery Network (PDN) design which resulted in better Floorplan efficiency.Clock tree development addressed cell density hot spots and skew reduction. Addressed early routability of design in reduced die area including lesser net detours.Addressed early IR/EM, Custom Route and DRC-Max density signoff checks. Addressed various techniques in STA to reduce Timing ECO cycles to achieve schedule
Technical challenges faced during Floorplan and Clock tree optimizations which led to timely Tapeout with better-than-expected quality of results.Some of the methods and Techniques were re used in projects of similar complexities and size.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall