Presentation
Accelerating analog connectivity verification with Jasper: comparing formal methods to mixed simulation
DescriptionEnsuring reliable connectivity between digital logic and analog IPs in ASIC design is a critical challenge in verification flows.
This paper introduces a novel approach leveraging formal verification with Jasper Connectivity to address the limitations of traditional mixed simulation methods. By automating the generation of connectivity assertions and utilizing a formal verification engine, we achieve comprehensive and exhaustive verification, significantly reducing setup and runtime.
Our methodology involves extracting netlists from analog schematic views, generating SystemVerilog assertions using Python scripts and proving the assertions with formal verification. This automated process not only accelerates verification but also enhances bug detection and ensures complete coverage. A comparative analysis shows that formal verification with Jasper is up to 1400 times faster in setup and 650 times faster in runtime compared to mixed simulations. Moreover, formal verification can identify bugs that mixed simulation could miss, highlighting its superior effectiveness.
The adoption of formal verification and Jasper Connectivity in our verification flow demonstrates substantial improvements in efficiency and quality assurance.
This approach ensures a bug-free connectivity between the analog and the digital world, enhancing silicon quality. The paper discusses the implementation, benefits, and impact of this innovative verification methodology on the overall design process.
This paper introduces a novel approach leveraging formal verification with Jasper Connectivity to address the limitations of traditional mixed simulation methods. By automating the generation of connectivity assertions and utilizing a formal verification engine, we achieve comprehensive and exhaustive verification, significantly reducing setup and runtime.
Our methodology involves extracting netlists from analog schematic views, generating SystemVerilog assertions using Python scripts and proving the assertions with formal verification. This automated process not only accelerates verification but also enhances bug detection and ensures complete coverage. A comparative analysis shows that formal verification with Jasper is up to 1400 times faster in setup and 650 times faster in runtime compared to mixed simulations. Moreover, formal verification can identify bugs that mixed simulation could miss, highlighting its superior effectiveness.
The adoption of formal verification and Jasper Connectivity in our verification flow demonstrates substantial improvements in efficiency and quality assurance.
This approach ensures a bug-free connectivity between the analog and the digital world, enhancing silicon quality. The paper discusses the implementation, benefits, and impact of this innovative verification methodology on the overall design process.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall