Presentation
Efficient Translation of OpenAccess Design Data to the OASIS® Format
DescriptionA frequent and critical step in layout design and chip integration verification is the conversion of design data from Open Access, a format suitable for editors and construction tools, to OASIS®, the format used by design rule checking, logic-to-schematic verification, and manufacturing mask creation. We present a method for distributed generation and rapid merging of OASIS and show how we achieved translation times of under 10 minutes for full-chip OASIS generation, compared to 5 hours using the prior tool. This reduction in runtime enabled an effective doubling of final closure design throughput, reducing schedule pressure and increasing design integration productivity.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall