Presentation
An Efficient Hierarchical Chip-Top Level EMIR Signoff Methodology for Large Automotive SOCs.
DescriptionThe increasing functionality and complexity of large automotive SoCs at 5nm FinFET has led to growing power grid complexity, creating challenges for efficient chip-top EMIR signoff. These automotive SoCs have billions of transistors, multiple power domains, several PVT corners, and operation modes, requiring comprehensive full-chip signoff within tight tape-out timeframes. Current methodologies for full-chip flat EMIR analysis have extremely high runtimes typically taking 1-3 days, 100's of cores and 50-100 GB peak memory per core for a single iteration. Divide and Conquer techniques do not apply here because of systematic inaccuracies, false EMIR violations and lengthy results consolidation. Full-chip level run failures result in higher cost per run both in terms of TAT and compute resources.
We present here a hierarchical methodology utilizing reduced order modelling, and the results using this methodology to achieve significant improvements in runtime and memory. We also compared the results from this hierarchical methodology with the full-chip flat analysis to verify that this hierarchical methodology has little to no compromise on accuracy of chip-top results. Our results from a large automotive SoC show a 2.4X performance improvement, 1.55X complexity reduction, and 2X memory savings, with accuracy deviations within 5% of flat analysis.
We present here a hierarchical methodology utilizing reduced order modelling, and the results using this methodology to achieve significant improvements in runtime and memory. We also compared the results from this hierarchical methodology with the full-chip flat analysis to verify that this hierarchical methodology has little to no compromise on accuracy of chip-top results. Our results from a large automotive SoC show a 2.4X performance improvement, 1.55X complexity reduction, and 2X memory savings, with accuracy deviations within 5% of flat analysis.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall