Presentation
Power-aware DFT-driven High Confidence EMIR Signoff for Low Power Automotive SoCs
DescriptionDue to enhanced circuit gating and redundant architectures, automotive-grade low-power integrated circuits exhibit increased susceptibility to IR-drop. The stringent reliability and stability requirements imposed by automotive applications across a wide range of voltage and temperature conditions, including extreme working conditions. Necessitate robust Design-for-Test (DFT) methodologies. Consequently, IR-drop analysis during DFT has become increasingly challenging and difficult to converge.
This paper provides a systematic overview of DFT optimization methods in low-power design. Leveraging power-aware DFT-driven EM/IR analysis, it proposes enhancement strategies to address IR hotspots. Focusing on DFT, the paper examines techniques like Q-gating, clock staggering, partitioning, one-hot scan chains, and memory bypass signals for X-state management, analyzing their effectiveness in reducing IR-drop and comprehensively discussing the challenges associated with low-power automotive chip sign-off.
This paper provides a systematic overview of DFT optimization methods in low-power design. Leveraging power-aware DFT-driven EM/IR analysis, it proposes enhancement strategies to address IR hotspots. Focusing on DFT, the paper examines techniques like Q-gating, clock staggering, partitioning, one-hot scan chains, and memory bypass signals for X-state management, analyzing their effectiveness in reducing IR-drop and comprehensively discussing the challenges associated with low-power automotive chip sign-off.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall