Presentation
Physical Design Independent-IR solver for early first cut SoC PG analysis
DescriptionTraditional SoC Power Grid (PG) design is iterative, requiring time-consuming analysis with commercial tools and multiple PnR cycles. This work presents a fast, automated PG synthesis and IR drop solver using a Python framework, enabling early-stage SoC analysis.The framework takes a PG specification as input, constructs a resistor-via mesh, generates a SPICE netlist, and employs a sparse matrix solver for rapid IR drop evaluation. This allows quick evaluation of various PG specifications, simulating different current distributions and mixed-PG regions.
Comparison with post-PnR sign-off analysis shows close approximation in IR histograms and heat-maps, validating the accuracy of the proposed method.The solver achieves a significant speedup of at least 10X in runtime and user effort compared to the conventional PnR-dependent flow.
The maximum error is approximately 1.5 mV for always-on and 10 mV for switchable grids, demonstrating acceptable accuracy for early-stage analysis.
This approach enables early assessment of PG grid templates, significantly accelerating PG design and optimization before PnR implementation.
Comparison with post-PnR sign-off analysis shows close approximation in IR histograms and heat-maps, validating the accuracy of the proposed method.The solver achieves a significant speedup of at least 10X in runtime and user effort compared to the conventional PnR-dependent flow.
The maximum error is approximately 1.5 mV for always-on and 10 mV for switchable grids, demonstrating acceptable accuracy for early-stage analysis.
This approach enables early assessment of PG grid templates, significantly accelerating PG design and optimization before PnR implementation.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall