Presentation
Peak Power Optimization in RTL2GDS flow using guidance from RTL Power Optimization tools
DescriptionIn contemporary chip design process, both Average and Peak power are important metrices. With more focus on average power, the power optimization techniques that save peak power are often neglected. This leads to critical issues in the downstream flows, as well as increases the cost of packaging for thermal management. Currently, no automated solution exists that can reduce peak power in the chip designing process.
In this paper, we propose a peak power optimization technique by re-scheduling the data-path operators across cycles in the RTL2GDS flow. This technique is similar to the retiming flow. However, the guidance from the RTL Power Optimization tool, based on data-path operator activity profile in the peak power region is consumed in the RTL2GDS flow. To enable this technique, a new optimization was added in the RTL2GDS flow that takes guidance from the RTL tool as an additional input. Using the existing and the modified RTL2GSD flows, two netlists were generated that were compared to validate the impact on Peak Power.
The results indicate that the design can be closed with lower peak power. Also, there was no noticeable impact on other PPA metrics of the design.
In this paper, we propose a peak power optimization technique by re-scheduling the data-path operators across cycles in the RTL2GDS flow. This technique is similar to the retiming flow. However, the guidance from the RTL Power Optimization tool, based on data-path operator activity profile in the peak power region is consumed in the RTL2GDS flow. To enable this technique, a new optimization was added in the RTL2GDS flow that takes guidance from the RTL tool as an additional input. Using the existing and the modified RTL2GSD flows, two netlists were generated that were compared to validate the impact on Peak Power.
The results indicate that the design can be closed with lower peak power. Also, there was no noticeable impact on other PPA metrics of the design.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall