Presentation
Automated – BUS Routing Solution for Efficient DRC clean TestChip Design
DescriptionA lot of automation is done for placement from block to top level. For routing, the implementation requirements can be much more complex and specific to design. Depending on whether routing is done for single net, bus or stacked bus routing, a lot of customization is required to meet the specifications. Additionally, there are multiple constraints to be considered, for example, DRCs, parasitic, area, current density and so on. At TestChip level, order of 100s of bits need to be routed in DRC correct manner. Critical nets such as CLK Tree, routing, need to be completed before routing other nets. Bus nets and symmetrical nets should be routed in similar topology.
An amalgamation of automatic and interactive routing is proposed in this paper to tackle TestChip routing of 100-200 nets efficiently. In this paper, we introduce a new integrated methodology of doing bus routing in Virtuoso Studio Layout Design - Cadence.
We have developed automated and interactive solutions- with flight lines, to show the connectivity between the block, to achieve first time correct DRC routing of 100-150 of nets, with minimum double via connect.
An amalgamation of automatic and interactive routing is proposed in this paper to tackle TestChip routing of 100-200 nets efficiently. In this paper, we introduce a new integrated methodology of doing bus routing in Virtuoso Studio Layout Design - Cadence.
We have developed automated and interactive solutions- with flight lines, to show the connectivity between the block, to achieve first time correct DRC routing of 100-150 of nets, with minimum double via connect.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall