Presentation
18% Die area reduction in UWB Automotive Production SoC meeting performance
DescriptionThe quest for miniaturization in chip design for automotive SOC applications like UWB smart keyfobs, is fraught with challenges that can inflate die size and compromise PPA target and efficiency aligned to product specification
Challenge-1 was Synthesis methodology gaps in reducing logic as timing optimization was not physical aware , was done in only functional mode (not in Test modes) and disablement of boundary optimization
Challenge-2 was to reduce Floorplan Overheads with respect to custom routing and DRV channel estimation and in multi power domain & mixed signal SoC having 35 Analog IPs in which 100 custom routes need to be implemented
Challenge-3 was to implement optimal power domain to avoid long routed signal nets through secondary domain and also mitigated crosstalk issues by allowing load splitting
Challenge-4 was to do custom placement of clock module logic coupled with refined modular placement which helped in robust Clock Tree development
Challenge-5 observed higher insertion delay due to higher logic depth at clock sources resulting in high cell density due to over bufferization.
Challenge-6 is to meet stringent Metal Tapeout(MTO/BEOL) timelines
Challenge-1 was Synthesis methodology gaps in reducing logic as timing optimization was not physical aware , was done in only functional mode (not in Test modes) and disablement of boundary optimization
Challenge-2 was to reduce Floorplan Overheads with respect to custom routing and DRV channel estimation and in multi power domain & mixed signal SoC having 35 Analog IPs in which 100 custom routes need to be implemented
Challenge-3 was to implement optimal power domain to avoid long routed signal nets through secondary domain and also mitigated crosstalk issues by allowing load splitting
Challenge-4 was to do custom placement of clock module logic coupled with refined modular placement which helped in robust Clock Tree development
Challenge-5 observed higher insertion delay due to higher logic depth at clock sources resulting in high cell density due to over bufferization.
Challenge-6 is to meet stringent Metal Tapeout(MTO/BEOL) timelines
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall